参数资料
型号: THS4271DRBT
厂商: TEXAS INSTRUMENTS INC
元件分类: 音频/视频放大
英文描述: 1 CHANNEL, VIDEO AMPLIFIER, PDSO8
封装: EXPOSED PAD, LEADLESS, PLASTIC, MSOP-8
文件页数: 21/48页
文件大小: 1227K
代理商: THS4271DRBT
SLOS397F – JULY 2002 – REVISED OCTOBER 2009
www.ti.com
BOARD LAYOUT GUIDELINES
performance.
Good
axial
metal-film
or
surface-mount resistors have approximately 0.2
Achieving
optimum
performance
with
a
pF in shunt with the resistor. For resistor values >
high-frequency amplifier like the THS4271 requires
2 k
, this parasitic capacitance can add a pole
careful attention to board layout parasitics and
and/or a zero below 400-MHz that can effect
external component types.
circuit operation. Keep resistor values as low as
possible,
consistent
with
load
driving
Recommendations that optimize performance include:
considerations. A good starting point for design is
1. Minimize parasitic capacitance to any ac
to set the Rf to 249- for low-gain, noninverting
ground for all of the signal I/O pins. Parasitic
applications. Doing this automatically keeps the
capacitance on the output and inverting input pins
resistor noise terms low, and minimizes the effect
can cause instability: on the noninverting input, it
of their parasitic capacitance.
can react with the source impedance to cause
4. Connections to other wideband devices on
unintentional band limiting. To reduce unwanted
the board may be made with short direct
capacitance, a window around the signal I/O pins
traces or through onboard transmission lines.
should be opened in all of the ground and power
For short connections, consider the trace and the
planes around those pins. Otherwise, ground and
input to the next device as a lumped capacitive
power planes should be unbroken elsewhere on
load. Relatively wide traces (50 mils to 100 mils)
the board.
should be used, preferably with ground and
2. Minimize the distance (< 0.25”) from the
power planes opened up around them. Estimate
power supply pins to high frequency 0.1-
μF
the total capacitive load and set RISO from the
de-coupling capacitors. At the device pins, the
plot of recommended RISO vs capacitive load.
ground and power plane layout should not be in
Low parasitic capacitive loads (<4 pF) may not
close proximity to the signal I/O pins. Avoid
need an R(ISO), since the THS4271 is nominally
narrow power and ground traces to minimize
compensated to operate with a 2-pF parasitic
inductance between the pins and the decoupling
load. Higher parasitic capacitive loads without an
capacitors. The power supply connections should
R(ISO) are allowed as the signal gain increases
always be decoupled with these capacitors.
(increasing the unloaded phase margin). If a long
Larger (2.2-
μF to 6.8-μF) decoupling capacitors,
trace is required, and the 6-dB signal loss
effective at lower frequency, should also be used
intrinsic to a doubly-terminated transmission line
on the main supply pins. These may be placed
is acceptable, implement a matched impedance
somewhat farther from the device and may be
transmission line using microstrip or stripline
shared among several devices in the same area
techniques (consult an ECL design handbook for
of the PCB.
microstrip and stripline layout techniques). A
3. Careful selection and placement of external
50-
environment is normally not necessary
components preserves the high frequency
onboard,
and
in
fact,
a
higher
impedance
performance of the THS4271. Resistors should
environment improves distortion as shown in the
be a very low reactance type. Surface-mount
distortion versus load plots. With a characteristic
resistors work best and allow a tighter overall
board trace impedance defined based on board
layout.
Metal-film
and
carbon
composition,
material and trace dimensions, a matching series
axially-leaded resistors can also provide good
resistor into the trace from the output of the
high frequency performance. Again, keep their
THS4271 is used as well as a terminating shunt
leads and PC board trace length as short as
resistor at the input of the destination device.
possible. Never use wire-wound type resistors in
Remember also that the terminating impedance is
a high frequency application. Since the output pin
the parallel combination of the shunt resistor and
and inverting input pin are the most sensitive to
the input impedance of the destination device:
parasitic
capacitance,
always
position
the
this total effective impedance should be set to
feedback and series output resistor, if any, as
match
the
trace
impedance.
If
the
6-dB
close as possible to the output pin. Other network
attenuation of a doubly terminated transmission
components,
such
as
noninverting
line is unacceptable, a long trace can be
input-termination resistors, should also be placed
series-terminated at the source end only. Treat
close
to
the
package.
Where
double-side
the trace as a capacitive load in this case and set
component
mounting
is
allowed,
place
the
the series resistor value as shown in the plot of
feedback resistor directly under the package on
R(ISO) vs capacitive load. This does not preserve
the other side of the board between the output
signal integrity or a doubly-terminated line. If the
and inverting input pins. Even with a low parasitic
input impedance of the destination device is low,
capacitance
shunting
the
external
resistors,
there is some signal attenuation due to the
excessively high resistor values can create
voltage divider formed by the series output into
significant time constants that can degrade
the terminating impedance.
28
Copyright 2002–2009, Texas Instruments Incorporated
Product Folder Link(s): THS4271 THS4275
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