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参数资料
| 型号： | THS7303PWRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 音频／视频放大 |
| 英文描述： | 3 CHANNEL, VIDEO AMPLIFIER, PDSO20 |
| 封装： | GREEN, PLASTIC, TSSOP-20 |
| 文件页数： | 35/60页 |
| 文件大小： | 1980K |
| 代理商： | THS7303PWRG4 |
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A =No Acknowledge(SDA High)
A = Acknowledge
S=StartCondition
P =StopCondition
W=Write
R=Read
A
P
DATA
S
Slave Address
FromTransmitter
FromReceiver
W
A6
A5
2
A0
A1
ACK
Acknowledge
(FromReceiver)
ICDevice Addressand
Read/WriteBit
R/W
D7
D6
D0
ACK
Stop
Condition
Acknowledge
(Receiver)
LastDataByte
SDA
D7
D6
D1
FirstData
Byte
Start
Condition
Acknowledge
(Transmitter)
ACK
Other
DataBytes
A =No Acknowledge(SDA High)
A = Acknowledge
S=StartCondition
P =StopCondition
W=Write
R=Read
A
P
DATA
S
Slave Address
Transmitter
Receiver
R
A6
2
A0
ACK
Acknowledge
(From
Receiver)
ICDevice Addressand
Read/WriteBit
R/W
D7
D0
ACK
Stop
Condition
Acknowledge
(From
Transmitter)
LastDataByte
SDA
D7
D6
D1
D0
ACK
FirstData
Byte
Start
Condition
Not
Acknowledge
(Transmitter)
Other
DataBytes
SLOS479B
– OCTOBER 2005 – REVISED MARCH 2011
During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its
address. Following this initial acknowledge by the slave, the master device becomes a receiver and
acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from
the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before
it asserts the stop condition. This sequence terminates a read cycle, as shown in Figure 77 and Figure 78. Note
that the THS7303 does not allow multiple read transfers to occur. See the Example: Reading from the THS7303
section for the proper procedure on reading from the THS7303.
Figure 75. I2C Write Cycle
Figure 76. Multiple Byte Write Transfer
Figure 77. I2C Read Cycle
Figure 78. Multiple Byte Read Transfer
40
Copyright
2005–2011, Texas Instruments Incorporated
Product Folder Link(s): THS7303
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