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参数资料
| 型号： | TK61220AQ4 |
| 厂商： | TOKO INC |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING REGULATOR, QCC24 |
| 封装： | 4 X 4 MM, HQFN-24 |
| 文件页数： | 7/23页 |
| 文件大小： | 342K |
| 代理商： | TK61220AQ4 |
TK61220AQ4
GC3-N008B
Page 15
11. APPLICATIONS INFORMATION
11-1. Timer Latch
The output of the FET over-current protection and the
LED
over-current
protection
and
the
over-voltage
protection are connected, count time is 1/fosc
×240. It can
be resumed by either turning EN pin voltage off and on or
by restoring supply voltage.
11-2. FET Overcurrent Protection
The TK61220AQ4 has built in FET over-current
protection and can set the maximum current of the
external FET by ISWMAX=0.1/RIS. When the IS pin voltage
exceeds 0.1V, the driver output turns Off, and the timer
latch starts counting. If it recovers while the timer is
counting, the driver output turns On again. If it doesn't
recover while the timer is counting, the timer latch
functions, and the driver output turns Off.
Even if the timer latch functions during a short between
VOUT-GND, and the driver output turns Off, the over-
current flows to the coil and the Schottky diode. If this
state continues for a long time, it may damage the coil
and the Schottky diode. If this is a concern, add the
circuit shown in figure 1.
The PGOOD pin changes to an "L" level when the timer
latch turns off the IC. The Pch FET at the input turns Off.
The route of the coil and Schottky diode is cut. The over-
current at the short state between VOUT-GND can be
limited.
Figure.1: Additional protection circuitry example 1
SW2
IS2
FB2
EAOUT2
17
15
14
13
18
PWM COMP 2
DRIVER 2
Vref
FET CURRENT
SENSE 2
DTC
T-LATCH 2
100mV
EAOUT
ERROR AMP 2
DIM T-LATCH 2
OSC
OVP AMP2
OUT
TIMER
LATCH 2
R1
C1
R2
R
IS
TR
R
LED
C
OUT
C
IN
V
FB
D
L
V
OUT
V
IN
On/Off
PGOOD2
11-2-1.The IS pin setting
Because the threshold voltage of FET over-current
protection is low (0.1V), the GND location of RIS should
be as close as possible to the IC GND. This will help
reduce possible noise generation. In addition, please use
wide traces because a considerable current flows in RIS.
When an inrush current is generated during the start up
and PWM dimming, there is a possibility of enabling the
FET
over-current
protection.
Please
adjust
the
capacitance at the error amplifier to eliminate any inrush
current during start up time.
In addition, when gate capacitance of the FET is large,
the charge current of the gate flows to RIS for a short time,
and there is the possibility of the FET over-current
protection malfunctioning. In this case please add a RC
filter.
Figure.2: RC filter constitution example
SW2
IS2
17
18
PWM COMP 2
DRIVER 2
FET CURRENT
SENSE 2
DTC
T-LATCH 2
100mV
EAOUT2
DIM T-LATCH 2
OSC
OVP AMP2
OUT
R
IS
TR
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