参数资料
型号: TL431CDR2G
厂商: ON Semiconductor
文件页数: 11/18页
文件大小: 0K
描述: IC VREF SHUNT PREC ADJ 8-SOICN
标准包装: 1
基准类型: 旁路,可调节,精度
输出电压: 2.495 V ~ 36 V
容差: ±2.2%
温度系数: 标准值 50ppm/°C
输入电压: 2.495 V ~ 36 V
通道数: 1
电流 - 阴极: 1mA
电流 - 输出: 100mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 标准包装
产品目录页面: 1127 (CN2011-ZH PDF)
其它名称: TL431CDR2GOSDKR
TL431, A, B Series, NCV431A, B
APPLICATIONS INFORMATION
P2 P2
The TL431 is a programmable precision reference which
is used in a variety of ways. It serves as a reference voltage
in circuits where a non ? standard reference voltage is
P2 +
2 p R
1
C
+
1
2 p * 10 M * 0.265 pF
+ 60 kHz
+ 500 kHz
Z1 +
+
2 p R C 2 p * 15.9 k * 20 pF
P +
L L
needed. Other uses include feedback control for driving an
optocoupler in power supplies, voltage monitor, constant
current source, constant current sink and series pass
regulator. In each of these applications, it is critical to
maintain stability of the device at various operating currents
and load capacitances. In some cases the circuit designer can
estimate the stabilization capacitance from the stability
boundary conditions curve provided in Figure 15. However,
these typical curves only provide stability information at
specific cathode voltages and at a specific load condition.
1 1
Z1 P1
In addition, there is an external circuit pole defined by the
load:
1
L 2 p R C
Also, the transfer dc voltage gain of the TL431 is:
G + G R GoR
Additional information is needed to determine the
capacitance needed to optimize phase margin or allow for
process variation.
Example 1:
M GM
L
I + 10 mA, R + 230 W , C + 0. Define the transfer gain.
G + G R GoR +
A simplified model of the TL431 is shown in Figure 31.
When tested for stability boundaries, the load resistance is
150 W . The model reference input consists of an input
transistor and a dc emitter resistance connected to the device
anode. A dependent current source, Gm, develops a current
whose amplitude is determined by the difference between
the 1.78 V internal reference voltage source and the input
C L L
The DC gain is:
M GM L
(2.138)(1.0 M)(1.25 m )(230) + 615 + 56 dB
transistor emitter voltage. A portion of Gm flows through
compensation capacitance, C P2 . The voltage across C P2
drives the output dependent current source, Go, which is
Loop gain + G
8.25 k
8.25 k ) 15 k
+ 218 + 47 dB
1 )
1 )
1 )
connected across the device cathode and anode.
Model component values are:
V ref = 1.78 V
Gm = 0.3 + 2.7 exp ( ? I C /26 mA)
where I C is the device cathode current and Gm is in mhos
Go = 1.25 (V cp 2) m mhos.
Resistor and capacitor typical values are shown on the
model. Process tolerances are ± 20% for resistors, ± 10% for
capacitors, and ± 40% for transconductances.
An examination of the device model reveals the location
of circuit poles and zeroes:
The resulting transfer function Bode plot is shown in
Figure 32. The asymptotic plot may be expressed as the
following equation:
jf
500 kHz
Av + 615
jf jf
8.0 kHz 60 kHz
The Bode plot shows a unity gain crossover frequency of
approximately 600 kHz. The phase margin, calculated from
the equation, would be 55.9 degrees. This model matches the
Open ? Loop Bode Plot of Figure 12. The total loop would
P1 +
2 p R
1
GM
C
P1
+
1
2 p * 1.0 M * 20 pF
+ 7.96 kHz
have a unity gain frequency of about 300 kHz with a phase
margin of about 44 degrees.
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