参数资料
型号: TL594CDTBR2
厂商: ON Semiconductor
文件页数: 5/12页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 16TSSOP
产品变化通告: Product Obsolescence 14/Apr/2010
标准包装: 2,500
系列: SWITCHMODE™
PWM 型: 电压模式
输出数: 1
频率 - 最大: 300kHz
占空比: 50%
电源电压: 7 V ~ 40 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
包装: 带卷 (TR)
TL594
APPLICATIONS INFORMATION
Description
The TL594 is a fixed?frequency pulse width modulation
control circuit, incorporating the primary building blocks
required for the control of a switching power supply. (See
Figure 1) An internal?linear sawtooth oscillator is frequency?
programmable by two external components, R T and C T . The
approximate oscillator frequency is determined by:
common?mode input range from ?0.3 V to (V CC ? 2 V), and
may be used to sense power?supply output voltage and
current. The error?amplifier outputs are active high and are
ORed together at the noninverting input of the pulse?width
modulator comparator. With this configuration, the
amplifier that demands minimum output on time, dominates
control of the loop.
f osc ≈
1.1
R T ? C T
For more information refer to Figure 3.
Output pulse width modulation is accomplished by
comparison of the positive sawtooth waveform across
Input/Output
Controls
Grounded
@ V ref
Functional Table
Output Function
Single?ended PWM @ Q1 and Q2
Push?pull Operation
f out
f osc =
1.0
0.5
capacitor C T to either of two control signals. The NOR gates,
which drive output transistors Q1 and Q2, are enabled only
when the flip?flop clock?input line is in its low state. This
happens only during that portion of time when the sawtooth
voltage is greater than the control signals. Therefore, an
increase in control?signal amplitude causes a corresponding
linear decrease of output pulse width. (Refer to the Timing
Diagram shown in Figure 2.)
The control signals are external inputs that can be fed into
the deadtime control, the error amplifier inputs, or the
feedback input. The deadtime control comparator has an
effective 120 mV input offset which limits the minimum
output deadtime to approximately the first 4% of the
sawtooth?cycle time. This would result in a maximum duty
cycle on a given output of 96% with the output control
grounded, and 48% with it connected to the reference line.
Additional deadtime may be imposed on the output by
setting the deadtime?control input to a fixed voltage,
ranging between 0 V to 3.3 V.
The pulse width modulator comparator provides a means
for the error amplifiers to adjust the output pulse width from
the maximum percent on?time, established by the deadtime
control input, down to zero, as the voltage at the feedback
pin varies from 0.5 V to 3.5 V. Both error amplifiers have a
500 k
When capacitor C T is discharged, a positive pulse is
generated on the output of the deadtime comparator, which
clocks the pulse?steering flip?flop and inhibits the output
transistors, Q1 and Q2. With the output?control connected
to the reference line, the pulse?steering flip?flop directs the
modulated pulses to each of the two output transistors
alternately for push?pull operation. The output frequency is
equal to half that of the oscillator. Output drive can also be
taken from Q1 or Q2, when single?ended operation with a
maximum on?time of less than 50% is required. This is
desirable when the output transformer has a ringback
winding with a catch diode used for snubbing. When higher
output?drive currents are required for single?ended
operation, Q1 and Q2 may be connected in parallel, and the
output?mode pin must be tied to ground to disable the
flip?flop. The output frequency will now be equal to that of
the oscillator.
The TL594 has an internal 5.0 V reference capable of
sourcing up to 10 mA of load current for external bias
circuits. The reference has an internal accuracy of ± 1.5%
with a typical thermal drift of less than 50 mV over an
operating temperature range of 0 ° to 70 ° C.
120
100 k
10 k
C T = 0.001 m F
0.01 m F
V CC = 15 V
110
100
90
80
70
60
50
40
A VOL
V CC = 15 V
D V O = 3.0 V
R L = 2.0 k W
φ
0
20
40
60
80
100
30
120
1.0 k
0.1 m F
20
10
140
160
500
1.0 k 2.0 k 5.0 k
10 k 20 k 50 k 100 k 200 k
500 k 1.0 M
0
1.0
10
100 1.0 k 10 k
100 k
180
1.0 M
R T, TIMING RESISTANCE ( W )
Figure 3. Oscillator Frequency versus
Timing Resistance
http://onsemi.com
5
f, FREQUENCY (Hz)
Figure 4. Open Loop Voltage Gain and
Phase versus Frequency
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