参数资料
型号: TLC1543QFNR
厂商: TEXAS INSTRUMENTS INC
元件分类: ADC
英文描述: 11-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC20
封装: PLASTIC, LCC-20
文件页数: 5/32页
文件大小: 770K
代理商: TLC1543QFNR
www.ti.com
TIMING DIAGRAMS
Access Cycle B
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB
LSB
Previous Conversion Data
MSB
LSB
B3
B2
B1
B0
C3
B9
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Hi-Z State
1
2
3
4
5
6
7
8
9
10
1
I/O
CLOCK
DATA
OUT
ADDRESS
CS
(see Note A)
EOC
Access Cycle B
Shift in New Multiplexer Address;
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB
LSB
Previous Conversion Data
MSB
LSB
B3
B2
B1
B0
C3
B9
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Low Level
1
2
3
4
5
6
7
8
9
10
1
I/O
CLOCK
DATA
OUT
ADDRESS
CS
EOC
Initialize
(see Note A)
Must be High on Power Up
SLAS052G – MARCH 1992 – REVISED JANUARY 2006
PARAMETER MEASUREMENT INFORMATION (continued)
A.
To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the
internal system clock after CS
↓ before responding to control input signals. Therefore, no attempt should be made to
clock in an address until the minimum CS setup time has elapsed.
Figure 9. Timing for 10-Clock Transfer Using CS
A.
To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the
internal system clock after CS
↓ before responding to control input signals. Therefore, no attempt should be made to
clock in an address until the minimum CS setup time has elapsed.
Figure 10. Timing for 10-Clock Transfer Not Using CS
13
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