参数资料
型号: TLC1543QN
厂商: TEXAS INSTRUMENTS INC
元件分类: ADC
英文描述: 11-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP20
封装: ROHS COMPLIANT, PLASTIC, DIP-20
文件页数: 2/36页
文件大小: 748K
代理商: TLC1543QN
TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q
10BIT ANALOGTODIGITAL CONVERTERS WITH
SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS052F MARCH 1992 REVISED JANUARY 2004
10
WWW.TI.COM
operating characteristics over recommended operating free-air temperature range,
VCC = Vref+ = 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TLC1542C, I, or Q
±0.5
LSB
EL
Linearity error (see Note 6)
TLC1543C, I, or Q
±1
LSB
EL
Linearity error (see Note 6)
TLC1542M
±1
LSB
TLC1542C, I, or Q
See Note 2
±1
LSB
EZS
Zero-scale error (see Note 7)
TLC1543C, I, or Q
See Note 2
±1
LSB
EZS
Zero-scale error (see Note 7)
TLC1542M
See Note 2
±1
LSB
TLC1542C, I, or Q
See Note 2
±1
LSB
EFS
Full-scale error (see Note 7)
TLC1543C, I, or Q
See Note 2
±1
LSB
EFS
Full-scale error (see Note 7)
TLC1542M
See Note 2
±1
LSB
TLC1542C, I, or Q
±1
LSB
Total unadjusted error (see Note 8)
TLC1543C, I, or Q
±1
LSB
Total unadjusted error (see Note 8)
TLC1542M
±1
LSB
ADDRESS = 1011
512
Self-test output code (see Table 3 and Note 9)
ADDRESS = 1100
0
Self-test output code (see Table 3 and Note 9)
ADDRESS = 1101
1023
tconv
Conversion time
See timing diagrams
21
s
tc
Total cycle time (access, sample, and conversion)
See timing diagrams
and Note 10
21
+10 I/O
CLOCK
periods
s
tacq
Channel acquisition time (sample)
See timing diagrams
and Note 10
6
I/O
CLOCK
periods
tv
Valid time, DATA OUT remains valid after I/O CLOCK
See Figure 6
10
ns
td(I/O-DATA)
Delay time, I/O CLOCK
↓ to DATA OUT valid
See Figure 6
240
ns
td(I/O-EOC)
Delay time, tenth I/O CLOCK
↓ to EOC↓
See Figure 7
70
240
ns
td(EOC-DATA)
Delay time, EOC
↑ to DATA OUT (MSB)
See Figure 8
100
ns
All typical values are at TA = 25°C.
NOTES:
2. Analog input voltages greater than that applied to REF + convert as all ones (1111111111), while input voltages less than that applied
to REF convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref + Vref ); however,
the electrical specifications are no longer applicable.
6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
7. Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the
difference between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
9. Both the input address and the output codes are expressed in positive logic.
10. I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 6)
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