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参数资料
| 型号： | TLC2552CDGKRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封装： | PLASTIC, MSOP-8 |
| 文件页数： | 26/26页 |
| 文件大小： | 651K |
| 代理商： | TLC2552CDGKRG4 |
TLC2551, TLC2552, TLC2555
5-V, LOW-POWER, 12-BIT, 175/360 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS276D – MARCH 2000 – REVISED MAY 2003
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VDD
4.5
5
5.5
V
Positive external reference voltage input, VREFP (see Note 1)
2
VDD
V
Analog input voltage (see Note 1)
0
VDD
V
High level control input voltage, VIH
2.1
V
Low-level control input voltage, VIL
0.6
V
Setup time, CS falling edge before first SCLK falling edge,
tsu(CSL-SCLKL)
VDD = REF = 4.5 V
40
ns
Hold time, CS falling edge after SCLK falling edge, th(SCLKL-CSL)
5
ns
Delay time, delay from CS falling edge to FS rising edge td(CSL-FSH) (TLC2551 only)
0.5
7
SCLKs
Setup time, FS rising edge before SCLK falling edge, tsu(FSH-SCLKL) (TLC2551 only)
0.35
SCLKs
Hold time, FS hold high after SCLK falling edge, th(SCLKL-FSL) (TLC2551 only)
0.65
SCLKs
Pulse width CS high time, tw(H_CS)
100
ns
Pulse width FS high time, tw(H_FS) (TLC2551 only)
0.75
SCLKs
SCLK cycle time, VDD = 5.5 V to 4.5 V, tc(SCLK) (maximum tolerance of 40/60 duty cycle)
50
10000
ns
Pulse width low time, tw(L_SCLK)
0.4
0.6
SCLKs
Pulse width high time, tw(H_SCLK)
0.4
0.6
SCLKs
Hold time, hold from end of conversion to CS high, th(EOC-CSH)(EOCisinternal,indicatesendofconversion
time, tc)
0.05
s
Active CS cycle time to reset internal MUX to AIN0, t(Reset cycle) (TLC2552 only)
4
7
SCLKs
Delay time, delay from CS falling edge to SDO valid, td(CSL-SDOV)
VDD = REF = 4.5 V, 25-pF load
40
ns
Delay time, delay from FS falling edge to SDO valid, td(FSL-SDOV)
(TLC2551 only)
VDD = REF = 4.5 V, 25-pF load
1
ns
Delay time, delay from SCLK rising edge to SDO valid,
td(SCLKH-SDOV)
VDD = REF = 4.5 V, 25-pF load
11
ns
Delay time, delay from 17th SCLK rising edge to SDO 3-state,
td(SCLK17H-SDOZ)
VDD = REF = 4.5 V, 25-pF load
30
ns
Conversion time, tc
28
SCLKs
Sampling time, t(sample)
See Note 2
300
ns
Operating free air temperature TA
TLC2551/2/5C
0
70
°C
Operating free-air temperature, TA
TLC2551/2/5I
–40
85
°C
NOTES:
1. Analog input voltages greater than that applied to VREF convert as all ones (111111111111), while input voltages less than that applied
to GND convert as all zeros(000000000000).
2. Minimal t(sample) is given by 0.9 × 50 pF × (RS + 0.5 k), where RS is the source output impedance.
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| TLC2555CDGKRG4 | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
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| TLC2552EVM | 功能描述:数据转换 IC 开发工具 TLC2552 Eval Mod RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
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| TLC2552IDGK | 功能描述:模数转换器 - ADC 12-Bit 400 kSPS Dual Ch Auto Sweep RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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