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参数资料
| 型号： | TLC2578IPWRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封装： | GREEN, PLASTIC, TSSOP-24 |
| 文件页数： | 17/49页 |
| 文件大小： | 1137K |
| 代理商： | TLC2578IPWRG4 |
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TLC3574, TLC3578, TLC2574, TLC2578
5V ANALOG, 3/5V DIGITAL, 14/12BIT, 200KSPS, 4/8CHANNEL
SERIAL ANALOGTODIGITAL CONVERTERS WITH ±10V INPUTS
SLAS262C OCTOBER 2000 REVISED MAY 2003
24
WWW.TI.COM
conversion mode (continued)
SWEEP Mode (Mode 10): During each operation, all of the channels listed in the SWEEP SEQUENCE (D[4:3]
of CFR register) are sampled and converted one time according to the programmed sequence. The results are
stored in the FIFO. When the FIFO threshold is reached, an interrupt (INT) is generated, and the operation ends.
If the FIFO threshold is reached before all of the listed channels are visited, the remaining channels are ignored.
This allows the host to change the sweep sequence length. The mode 10 operation starts with the WRITE CFR
command to set the sweep sequence. The following triggers (CS, FS, or CSTART, depending on the interface)
start the samplings and conversions of the listed channels in sequence until the FIFO threshold is hit. If CS or
FS starts the sampling, the SDI data must be any one of the SELECT commands to set the converter in
conversion state. However, this command is a dummy code. It does not change the existing conversion
sequence. After the FIFO is full, the converter waits for FIFO READ. It does nothing before the FIFO READ or
WRITE CFR command is issued. The host must read the FIFO completely or WRITE CFR. If CSTART triggers
the samplings, the host must issue an extra SELECT/CONVERSION command (select any channel) via CS or
FS after the FIFO READ or WRITE CFR. This extra period is named the arm period and is used to set the
converter into conversion state, but does not affect the existing conversion sequence. If FS initiates the
operation and CSTART triggers the samplings and conversions, CS must not toggle during the conversion.
REPEAT SWEEP Mode (Mode 11): This mode works in the same way as mode 10, except that it is not
necessary to read the FIFO before the next operation after the FIFO threshold is hit. The next sweep can repeat
immediately, but the contents in the FIFO are replaced by the new results. The host can read the FIFO
completely, then issue next SWEEP; or repeat the SWEEP immediately (with the existing sweep sequence) by
issuing sampling/conversion triggers (CS, FS or CSTART); or change the device setting with the WRITE CFR
command.
The memory effect of charge redistribution DAC exists when the mux switches from one channel to another.
This degrades the channel-to-channel isolation if the channel changes after each conversion. For example, in
mode 10 and 11, the isolation is about 70 dB for the sweep sequence 0-1-2-3-4. The memory effect can be
reduced by increasing the sampling time or using sweep sequence 0-0-2-2-4-4-6-6 and ignoring the first sample
of each channel.
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| TLC2578IDWG4 | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| TLC2578IPWR | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
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