- 您现在的位置：买卖IC网 > PDF目录69493 > TLC2932IPWR (TEXAS INSTRUMENTS INC) PHASE LOCKED LOOP, 40 MHz, PDSO14 PDF资料下载
参数资料
| 型号： | TLC2932IPWR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 40 MHz, PDSO14 |
| 封装： | GREEN, PLASTIC, TSSOP-14 |
| 文件页数： | 8/28页 |
| 文件大小： | 665K |
| 代理商： | TLC2932IPWR |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MAY 1997
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
low-pass-filter (LPF) configurations
Many excellent references are available that include detailed design information about LPFs and should be
consulted for additional information. Lag-lead filters or active filters are often used. Examples of LPFs are shown
in Figure 25. When the active filter of Figure 25(c) is used, the reference should be applied to FIN-B because
of the amplifier inversion. Also, in practical filter implementations, C2 is used as additional filtering at the VCO
input. The value of C2 should be equal to or less than one tenth the value of C1.
R1
C1
T1 = C1R1
(a) LAG FILTER
R1
C1
T1 = C1R1
T2 = C1R2
R2
(b) LAG-LEAD FILTER
R2
C1
R1
T1 = C1R1
T2 = C1R2
(c) ACTIVE FILTER
A
–
VI
VO
VI
VO
VI
C2
VO
C2
Figure 25. LPF Examples for PLL
the passive filter
The transfer function for the lag-lead filter shown in Figure 25(b) is;
V
O
V
IN
+
1
) s
@ T2
1
) s
@ (T1 ) T2)
Where
T1
+ R1
@ C1 and T2 + R2 @ C1
Using this filter makes the closed loop PLL system a second-order type 1 system. The response curves of this
system to a unit step are shown in Figure 26.
the active filter
When using the active integrator shown in Figure 25(c), the phase detector inputs must be reversed since the
integrator adds an additional inversion. Therefore, the input reference frequency should be applied to the FIN-B
terminal and the output of the VCO divider should be applied to the input reference terminal, FIN-A.
The transfer function for the active filter shown in Figure 25(c) is:
F(s)
+ 1 ) s @ R2 @ C1
s
@ R1 @ C1
Using this filter makes the closed loop PLL system a second-order type 2 system. The response curves of this
system to a unit step are shown in Figure 27.
basic design example
The following design example presupposes that the input reference frequency and the required frequency of
the VCO are within the respective ranges of the device.
相关PDF资料 |
PDF描述 |
|---|---|
| TLC2933AIPWRG4 | PHASE LOCKED LOOP, 1 MHz, PDSO14 |
| TLC2942IDBR | PHASE LOCKED LOOP, 20 MHz, PDSO38 |
| TLC2942IDBLE | PHASE LOCKED LOOP, 20 MHz, PDSO38 |
| TLC32046IFN | SPECIALTY ANALOG CIRCUIT, PQCC28 |
| TLC32046MFKR | SPECIALTY ANALOG CIRCUIT, CQCC28 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TLC2932IPWRG4 | 功能描述:锁相环 - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| TLC2933AIPW | 功能描述:锁相环 - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| TLC2933AIPWG4 | 功能描述:锁相环 - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| TLC2933AIPWR | 功能描述:锁相环 - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| TLC2933AIPWRG4 | 功能描述:锁相环 - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
发布紧急采购，3分钟左右您将得到回复。