TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
VCO1, VCO2 operating characteristics, VDD = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fosc
Operating oscillation frequency
RBIAS1, RBIAS2 = 2.2 k,
VCOIN1, VCOIN2 = 1/2 VDD
32
41
50
MHz
ts(fosc)
Time to stable oscillation
See Note 8
10
s
t
Rise time
CL = 15 pF,
See Figure 3
5.5
10
ns
tr
Rise time
CL = 50 pF,
See Figure 3
8
ns
tf
Fall time
CL = 15 pF,
See Figure 3
5
10
ns
tf
Fall time
CL = 50 pF,
See Figure 3
6
ns
Duty cycle at VCO OUT
RBIAS1, RBIAS2 = 2.2 k,
VCOIN1, VCOIN2 = 1/2 VDD
45%
50%
55%
α(fosc)
Temperature coefficient of oscillation frequency
RBIAS1, RBIAS2 = 2.2 k,
VCOIN1, VCOIN2 = 1/2 VDD,
Tope = –20°C to 75°C
0.06
%/
°C
kSVS(fosc)
Supply voltage coefficient of oscillation fre-
quency
RBIAS1, RBIAS2 = 2.2 k,
VCOIN1, VCOIN2 = 2.5 V,
VDD = 4.75 V to 5.25 V
0.006
%/mV
Jitter absolute (see Note 9)
RBIAS1 = 3.3 k
100
ps
NOTES: 8.
The time period to stabilize the VCO oscillation frequency after VCOINHIBIT is changed to a low level.
9.
The LPF circuit is shown in Figure 28 with calculated values listed in Table 9. Jitter performance is highly dependent on circuit layout
and external device characteristics. The jitter specification was made with a carefully designed PCB with no device socket.
PFD1, PFD2 operating characteristics, VDD = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fmax
Maximum operating frequency
40
MHz
tPLZ
PFD output disable time from low level
21
40
ns
tPHZ
PFD output disable time from high level
See Figures 4 and 5 and Table 4
20
40
ns
tPZL
PFD output enable time to low level
See Figures 4 and 5 and Table 4
7.3
20
ns
tPZH
PFD output enable time to high level
6.5
20
ns
tr
Rise time
CL =15 pF
See Figure 4
2.3
10
ns
tf
Fall time
CL = 15 pF,
See Figure 4
1.7
10
ns