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参数资料
| 型号： | TLC2943IDB |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 55 MHz, PDSO38 |
| 封装： | PLASTIC, SSOP-38 |
| 文件页数： | 2/28页 |
| 文件大小： | 440K |
| 代理商： | TLC2943IDB |
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TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, VDD = 5 V
(unless otherwise noted) (continued)
VCO section
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VOH
High-level output voltage
IOH = – 2 mA
4.5
V
VOL
Low-level output voltage
IOL = 2 mA
0.5
V
V(TH+)
Positive input threshold voltage
1.5
2.5
3.5
V
II
Input current
VI = VDD or GND
±1
A
Z(VCOIN) VCOIN input impedance
VCOIN = 1/2VDD
10
M
IDD(INH)
VCO supply current (inhibit) (for one chip)
See Note 5
0.01
1
A
IDD(VCO) VCO supply current (for one chip)
See Note 6
14
35
mA
NOTES:
5. The current into VCO VDD and LOGIC VDD when VCO INHIBIT = VDD and PFD INHIBIT is high.
6. The current into VCO VDD and LOGIC VDD when VCO IN = 1/2 VDD , RBIAS = 2.4 k, VCO INHIBIT = ground, and PFD INHIBIT
is high.
PFD section
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VOH
High-level output voltage
IOH = – 2 mA
4.5
V
VOL
Low-level output voltage
IOL = 2 mA
0.2
V
IOZ
High-impedance state output current
PFD INHIBIT = high,
VO = VDD or GND
±1
A
VIH
High-level input voltage at FIN–A, FIN–B
3.5
V
VIL
Low-level input voltage at FIN–A, FIN–B
1.5
V
V(TH+)
Positive input threshold voltage at PFD
INHIBIT
1.5
2.5
3.5
V
CI
Input capacitance at FIN–A, FIN–B
7
pF
ZI
Input impedance at FIN–A, FIN–B
10
M
IDD(PFD)
PFD supply current
See Note 9
2.6
8
mA
NOTE 9: The current into LOGIC VDD when FIN–A and FIN–B = 50 MHz (V I(PP) = 5 V, rectangular wave), PFD INHIBIT = GND, PFD OUT open,
and VCO OUT is inhibited.
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