vi
List of Illustrations
Figure
Title
Page
2–1 Timing Sequence of ADC Channel (Primary Communication Only)
2–2
. . . . . .
2–2 Timing Sequence of ADC Channel (Primary and Secondary
Communication)
2–2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 Timing Sequence of DAC Channel (Primary Communication Only)
2–3
. . . . . .
2–4 Timing Sequence of DAC Channel (Primary and Secondary
Communication)
2–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 Register 1 Read Operation Timing Diagram
2–4
. . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 Register 1 Write Operation Timing Diagram
2–5
. . . . . . . . . . . . . . . . . . . . . . . . . .
2–7 Internal Power-Down Logic
2–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–8 Master Device Frame-Sync Signal With Primary and Secondary
Communications (No Slaves)
2–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–9 Master Device Frame-Sync Signal With Primary and Secondary
Communications (With 1 Slave Device)
2–8
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–10 Master Device FS and FSD Output When FSD Register (D0–D5,
Control 3 Register) is 0
2–9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–11 Master Device FS and FSD Output After Control 3 Register Is
Programmed (One Slave Device)
2–9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–12 Master With Slaves (To DSP Interface)
2–10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–13 Master-Slave Frame-Sync Timing After A Delay Has Been
Programmed Into The FSD Register (D0–D5 of Control 3 Register)
2–10
. . .
2–14 Master Device FS and FSD Output After Control 3 Register
Is Programmed With 49H
2–11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–15 RC Antialias Filter
2–11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–16 INP and INM Internal Self-Biased (2.5 V) Circuit
2–12
. . . . . . . . . . . . . . . . . . . . .
2–17 Differential Output Drive (Ground Referenced)
2–12
. . . . . . . . . . . . . . . . . . . . . . .
2–18 Digital Input Code vs Analog Output Voltage
2–12
. . . . . . . . . . . . . . . . . . . . . . . .
3–1 Primary Serial Communication Timing
3–1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 Hardware and Software Methods to Make a Secondary Request
3–2
. . . . . . . . .
3–3 FS Output When Hardware Secondary Serial Communication Is Requested
Only Once (No Slave)
3–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 FS Output When Hardware Secondary Serial Communication Is Requested
Only Once (Three Slaves)
3–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 FS Output During Software Secondary Serial Communication Request
(No Slave)
3–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–6 Phone Mode Timing When Phone Mode Is Enabled
3–4
. . . . . . . . . . . . . . . . . . .