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参数资料
| 型号： | TLC320AD55CDW |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封装： | PLASTIC, SOP-28 |
| 文件页数： | 7/41页 |
| 文件大小： | 203K |
| 代理商： | TLC320AD55CDW |
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2–3
2.1.13
FIR Overflow Flag
The decimator FIR filter provides an overflow flag to the control 2 register to indicate that the input to the
filter has exceeded the range of the internal filter calculations. When this bit is set in the register, it remains
set until the register is read by the user. Reading this value always resets the overflow flag.
2.2
Terminal Descriptions
The following sections describe the terminal functions.
2.2.1
Reset and Power-Down
2.2.1.1
Reset
As shown in Figure 2–1, the TLC320AD55C resets both the internal counters and registers, including the
programmed registers, in two ways:
By appling a low-going reset pulse to the RESET terminal
By writing to the programmable software reset bit (D07 in control 1 register)
PWRDWN resets the counters only and preserves the programmed register contents. The DAC resets to
the 15-bit mode.
RESET
D
TRESET
RESET
Software RESET Control
Register 1, Bit 7
MCLK
To Circuitry
NOTE A: RESET to circuitry is at least 6 MCLK periods long and releases on the positive edge of MCLK.
Internal TLC320AD55C
Figure 2–1. Reset Function
2.2.1.2
Conditions of Reset
The two internal reset signals used for the reset and synchronization functions are:
Counter reset
– This signal resets all flip-flops and latches that are not externally programmed,
with the exception of those generating the reset pulse itself. Additionally, this
signal resets the software power-down bit.
Counter reset
=RESET terminal or reset bit or PWRDWN terminal
Register reset
– This signal resets all flip-flops and latches that are not reset by the counter
reset, except those generating the reset pulse itself.
Register reset
=RESET terminal or reset bit
Both reset signals are at least six MCLK periods long (TRESET) and release on the trailing edge of MCLK.
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