参数资料
型号: TLC3541IDGKG4
厂商: TEXAS INSTRUMENTS INC
元件分类: ADC
英文描述: 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封装: GREEN, PLASTIC, MSOP-8
文件页数: 3/25页
文件大小: 648K
代理商: TLC3541IDGKG4
TLC3541, TLC3545
SLAS345 DECEMBER 2001
11
www.ti.com
PRINCIPLES OF OPERATION
control and timing
device initialization/RESET cycle
The TLC3541/45 each require one RESET cycle after power-on for initialization in order to operate properly.
The RESET cycle is initiated by asserting the CS pin (pin 1) low for a minimum duration of at least one SCLK
falling edge but no more than 8 SCLK falling edges in length. The RESET cycle is terminated by asserting CS
high. If a valid RESET cycle is issued, the data presented on the SDO output during the following cycle is 3FC0h.
This output code is useful in determining when a valid reset/initialization has occurred.
The TLC3541 has separate CS and FS pins. In this case, it is also possible to initiate the RESET cycle by
asserting FS low if CS is already asserted low. The RESET cycle can be terminated by either asserting CS high
(as shown in the first RESET cycle in Figure 14), or by asserting FS high (as shown in the second RESET cycle
in Figure 14), whichever happens first.
18 Falling SCLK Edges
ADC is Initialized
1
2
1
4
8
MSB
LSB+1
1
2
8
1
4
16
LSB
11111111000000XX
tcyc(reset)
SCLK
OR
tcyc(reset)
FS High for Valid Initialization
Normal CycleSample
and Convert
t(PWRDWN)
SDO DataReset of Previous Cycle’s Sample
For TLC35xxLSB Presented on 14th Rising SCLK Edge
Normal CycleSample
and Convert
CS
FS
SDO
Figure 14. TLC3541/45 Initialization Timing
sampling
The converter sample time is 20 SCLKs in duration, beginning on the 5th SCLK received during an active signal
on the CS input (or FS input for the TLC3541.)
conversion
Each device completes a conversion in the following manner. The conversion is started after the 24th falling
SCLK edge. The CS input can be released at this point or at any time during the remainder of the conversion
cycle. The conversion takes a maximum of 2.67
s to complete. Enough time (for conversion) should be allowed
before the next falling edge on the CS input (or rising edge on the FS input for the TLC3541) so that no
conversion is terminated prematurely. If the conversion cycle is terminated early, the data presented on SDO
during the following cycle is 3FC0h. This predefined output code is helpful in determining if the cycle time is not
long enough to complete the conversion. The same code is also used to determine if a reset cycle is valid.
For all devices, the SDO data presented during a cycle is the result of the conversion of the sample taken during
the previous cycle. The output data format is shown in the following table.
SERIAL OUTPUT DATA FORMAT
MSB [D15:D2]
LSB [D1:D0]
TLC3541/45
Conversion result (OD13OD0)
Don’t care
相关PDF资料
PDF描述
TLC3541IDRG4 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
TLC3541IDGK 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
TLC3545IDGK 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
TLC3545ID 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
TLC3544IDWRG4 4-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20
相关代理商/技术参数
参数描述
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TLC3541IDGKRG4 功能描述:模数转换器 - ADC 5V Lo-Pwr 14-Bit 200 KSPS Serial RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32
TLC3541IDR 功能描述:模数转换器 - ADC 5V Lo-Pwr 14-Bit 200 KSPS Serial RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32
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TLC3544 制造商:TI 制造商全称:Texas Instruments 功能描述:5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS