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参数资料
| 型号： | TLC3545IDGKRG4 |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | 5-V. LOW POWER, 14-BIT, 200-KSPS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTO-POWER DOWN |
| 中文描述： | 5 - V等。低功耗，14位200 ksps的串行模数位自动转换器掉电 |
| 文件页数： | 6/23页 |
| 文件大小： | 481K |
| 代理商： | TLC3545IDGKRG4 |
SLAS345 DECEMBER 2001
6
www.ti.com
timing requirements, V
DD
= 5 V, V
REF
= 4.096 V, SCLK frequency = 15 MHz (unless otherwise specified)
MIN
TYP
MAX
UNIT
tcyc(SCLK)
tw1
tw2
th1
tsu1
th2
tw3
td1
td2
td3
tsu3
tw4
tsu4
th4
tsu5
td4
th6
tsu6
th7
tsu7
tcyc(reset)
tconv
ts
NOTES:
SCLK cycle time, VDD = 4.5 V to 5.5 V (see Note 3)
Pulse duration, SCLK low
66
10000
ns
27
5000
ns
Pulse duration, SCLK high
27
5000
ns
Hold time, CS high after SCLK falling edge
3
ns
Setup time, CS falling edge before the first SCLK falling edge
15
ns
Hold time, CS low after 16th SCLK falling edge
5
ns
Pulse duration, CS high
0.5
SCLKs
Delay time, CS falling edge to SDO MSB valid, VDD = VREF = 4.5 V, 20 pF
Delay time, SCLK rising edge to next SDO data bit valid, VDD = VREF = 4.5 V, 20 pF
Delay time, 17th SCLK rising edge to 3-stated SDO, VDD = VREF = 4.5 V, 20 pF (see Note 4)
Setup time, CS falling edge before FS rising edge (TLC3541 only)
12
17
ns
15
ns
20
ns
0.5
1
SCLKs
Pulse duration, FS high (TLC3541 only)
0.5
1
SCLKs
Setup time, FS rising edge before SCLK falling edge (TLC3541 only)
12.5
ns
Hold time, FS high after SCLK falling edge (TLC3541 only)
5
ns
Setup time, FS falling edge before 1st SCLK falling edge (TLC3541 only)
12
ns
Delay time, FS rising edge to SDO MSB valid, (VDD = VREF = 4.5 V, 20 pF TLC3541 only)
Hold time, CS low after 1st SCLK falling edge
15
ns
5
ns
Setup time, CS rising edge before 9th (or the last) SCLK falling edge
5
ns
Hold time, FS low after 1st SCLK falling edge (TLC3541 only)
5
ns
Setup time, FS rising edge before 9th (or the last) SCLK falling edge
5
ns
Active CS/FS cycle time, SCLK falling edges required to initialize ADC
1
8
SCLKs
μ
s
μ
s
Conversion time (20 conversion clocks based on 7.5 MHz to 12 MHz OSC)
1.67
2.67
Sample time, 20 SCLKs, SCLK up to 15 MHz
3. Timing specifications given for 40/60 to 60/40 duty cycle
4. SDO goes into the high impedance state after detection of the 17th rising SCLK edge or a rising CS edge if a 17th SCLK is not
presented.
1.33
200
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TLC3545IDR | 功能描述:模数转换器 - ADC 14-Bit 200KSPS Serial Out RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TLC3545IDRG4 | 功能描述:模数转换器 - ADC 14-Bit 200KSPS Serial Out RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TLC3548 | 制造商:TI 制造商全称:Texas Instruments 功能描述:5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS |
| TLC3548CDW | 功能描述:模数转换器 - ADC 14-bit 5V 200KSPS 8-Channel Unipolar RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TLC3548CDWG4 | 功能描述:模数转换器 - ADC 14-bit 5V 200KSPS 8-Channel Unipolar RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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