参数资料
型号: TLC3545IDGKRG4
厂商: TEXAS INSTRUMENTS INC
元件分类: ADC
英文描述: 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封装: GREEN, PLASTIC, MSOP-8
文件页数: 5/26页
文件大小: 661K
代理商: TLC3545IDGKRG4
TLC3541, TLC3545
SLAS345 DECEMBER 2001
13
www.ti.com
PRINCIPLES OF OPERATION
control via pin 1 (CS, DSP interface)
All devices are compatible with this mode of operation. The FS signal from a DSP is connected directly to the
CS input of the ADC. A falling edge on the CS input while SCLK is high or low initiates the cycle. (For TLC3541
in this configuration, the FS input is tied to VDD.) Enough time should be allowed before the next rising CS edge
so that the conversion cycle is not terminated prematurely.
1
2
3
5
4
6
7
13
14
15
16
1
12
ts
tconv
t(PWRDWN)
SDO Data Is the Result of the Previous Sample
For TLC35xx, the LSB Is Presented on the Rising SCLK 14th Edge
MSB
MSB1
MSB2 MSB3 MSB4 MSB5 MSB6
LSB+2
LSB+1
LSB
LSB1
LSB2
SCLK
CS
SDO
MSB
MSB1
The CS Input Signal Is
Generated by the FS Output
From a TMS320 DSP
24
Figure 16. DSP Cycle Timing Using the CS Input (FS = 1 for TLC3541 only)
control via pin 1 and pin 7 (CS and FS or FS only, DSP interface)
Only TLC3541 is compatible with this mode of operation. The CS input to the ADC can be controlled via a
general-purpose I/O pin from the DSP or tied to ground. The FS signal from the DSP is connected directly to
the FS input of the ADC. A rising FS edge releases the MSB to the SDO output. The falling edge on the FS input
while SCLK is high or low initiates the cycle. The CS input should remain low for the entire sampling time plus
4 SCLK decoding time after falling FS (24 falling SCLK edges) and can then be released at any time during the
remainder of the conversion cycle. The optimum DSP interface is achieved when tying CS to ground and using
only the FS input to control the ADC.
tconv
t(PWRDWN)
SDO Data Is the Result of the Previous Sample
For TLC35xx, the LSB Is Presented on the Rising SCLK 14th Edge
1
2
3
5
4
6
14
15
16
1
2
34
ts
MSB
MSB1 MSB2 MSB3 MSB4 MSB5 LSB+1
LSB
LSB1 LSB2
MSB
MSB1 MSB2 MSB3
The MSB Is Presented on the SDO Output After
a Rising Edge on the FS Input.
17
24
The Device Will Go Into the Power Down State After the Conversion Is
Complete. A Falling CS Edge or Rising FS Edge, Whichever Occurs First,
Removes the Device From Power Down.
SCLK
CS
SDO
FS
Figure 17. DSP Cycle Timing Using FS Only (or Using Both CS and FS for TLC3541)
相关PDF资料
PDF描述
TLC3548CPW 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
TLC3548IDW 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
TLC3548IPW 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
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