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参数资料
| 型号： | TLC3548CDWRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封装： | GREEN, PLASTIC, SOIC-24 |
| 文件页数： | 44/44页 |
| 文件大小： | 1000K |
| 代理商： | TLC3548CDWRG4 |
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TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C – OCTOBER 2000 – REVISED MAY 2003
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, AVDD = 5 V,
DVDD
= 5 V, VREFP = 5 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted)
SCLK, SDI, SDO, EOC and INT
PARAMETERS
MIN
TYP
MAX
UNIT
t (1)
Cycle time of SCLK at 25 pF load
DVDD = 2.7 V
100
ns
tc(1)
Cycle time of SCLK at 25-pF load
DVDD = 5 V
40
ns
tw(1)
Pulse width, SCLK high time at 25-pF load
40%
60%
tc(1)
t
Rise time for INT EOC at 10 pF load
DVDD = 5 V
6
ns
tr(1)
Rise time for INT, EOC at 10-pF load
DVDD = 2.7 V
10
ns
t
Fall time for INT EOC at 10 pF load
DVDD = 5 V
6
ns
tf(1)
Fall time for INT, EOC at 10-pF load
DVDD = 2.7 V
10
ns
tsu(1)
Setup time, new SDI valid (reaches 90% final level) before falling edge of SCLK, at 25-pF
load
6
–
ns
th(1)
Hold time, old SDI hold (reaches 10% of old data level) after falling edge of SCLK, at
25-pF load
0
–
ns
t
Delay time, new SDO valid (reaches 90% of final level) after SCLK rising
DVDD= 5 V
0
10
ns
td(1)
Delay time, new SDO valid (reaches 90% of final level) after SCLK rising
edge, at 10-pF load
DVDD = 2.7 V
0
23
ns
th(2)
Hold time, old SDO hold (reaches 10% of old data level) after SCLK rising edge, at 10-pF
load
0
–
ns
td(2)
Delay time, delay from sixteenth SCLK falling edge to EOC falling edge, normal sampling,
at 10-pF load
0
6
ns
td(3)
Delay time, delay from the sixteenth falling edge of SCLK to INT falling edge, at 10-pF
load [see the () double dagger note and Note 6]
t(conv)
t(conv) + 6
s
The minimum pulse width of SCLK high is 12.5 ns. The minimum pulse width of SCLK low is 12.5 ns.
Specified by design
NOTE 6: For normal short sampling, td(3) is the delay from 16th falling edge of SCLK to INT falling edge.
For normal long sampling, td(3) is the delay from 48th falling edge of SCLK to the falling edge of INT.
Conversion time, t(conv) is equal to 18 × OSC + 15 ns when using internal OSC as conversion clock, or 72 × tc(1) + 15 ns when external
SCLK is conversion clock source.
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