参数资料
型号: TLC3548CPWRG4
厂商: TEXAS INSTRUMENTS INC
元件分类: ADC
英文描述: 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24
封装: GREEN, PLASTIC, TSSOP-24
文件页数: 17/44页
文件大小: 1000K
代理商: TLC3548CPWRG4
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C – OCTOBER 2000 – REVISED MAY 2003
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operation timing diagrams (continued)
12
3
5
46
7
13
14
15
16
1
ID15
1D14
ID13 1D12
12
ID15
ID14
ID11
ID10
ID9
ID4
ID3
ID2
ID1
ID0
OR
Note:
Signal May Not Exist.
Don’t Care
CS
FS = High
SDI
INT
EOC
SDO
Hi-Z
Figure 10. Write Cycle, CS Initiates Operation, FS = 1
FIFO Read Operation: When the FIFO is used, the first command after INT is generated is assumed to be the
FIFO read. The first FIFO content is sent out immediately before the command is decoded. If this command is
not a FIFO read, the output is terminated. Using more layers of the FIFO reduces the time taken to read multiple
conversion results, because the read cycle does not generate an EOC or INT, nor does it make a data
conversion. Once the FIFO is read, the entire contents in the FIFO must be read out. Otherwise, the remaining
data is lost.
12
3
5
46
7
13
14
15
16
1
ID15
1D14
ID13
1D12
OD11 OD10 OD9
OD4
OD3
OD2
12
ID15
ID14
OD15 OD14 OD13 OD12
OD15
OD14
OR
Notes:
Signal May Not Exist.
SCLK
CS
FS = High
SDI
INT
EOC
SDO
OD[15:2] is FIFO Contents.
Don’t Care
Hi-Z
Figure 11. FIFO Read Cycle, CS Initiates Operation, FS = 1
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