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参数资料
| 型号： | TLC540IFNRG3 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 11-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC20 |
| 封装： | GREEN, PLASTIC, LCC-20 |
| 文件页数： | 2/16页 |
| 文件大小： | 296K |
| 代理商： | TLC540IFNRG3 |
TLC540I, TLC541I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS065B – OCTOBER 1983 – REVISED JUNE 2001
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
It is possible to connect SYSTEM CLOCK and I/O clock together in special situations in which controlling circuitry
points must be minimized. In this case, the following special points must be considered in addition to the requirements
of the normal control sequence previously described.
1.
The first two clocks are required for this device to recognize CS is at a valid low level when the common clock
signal is used as an I/O CLOCK. When CS is recognized by the device to be at a high level, the common clock
signal is used for the conversion clock also.
2.
A low CS must be recognized before the I/O CLOCK can shift in an analog channel address. The device
recognizes a CS transition when the SYSTEM CLOCK terminal receives two positive edges and then a
negative edge. For this reason, after a CS negative edge, the first two clock cycles do not shift in the address.
Also, upon shifting in the address, CS must be raised after the eighth valid (10 total) I/O CLOCK. Otherwise,
additional common clock cycles are recognized as I/O CLOCKS and will shift in an erroneous address.
For certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time.
This device accommodates these applications. Although the on-chip sample and hold begins sampling upon the
negative edge of the fourth valid I/O clock cycle, the hold function is not initiated until the negative edge of the eighth
valid I/O clock cycle. Thus, the control circuitry can leave the I/O clock signal in its high state during the eighth valid
I/O clock cycle until the moment at which the analog signal must be converted. The TLC540/TLC541 continues
sampling the analog input until the eighth falling edge of the I/O clock. The control circuitry or software then
immediately lowers the I/O clock signal and holds the analog signal at the desired point in time and start conversion.
Detailed information on interfacing to most popular microprocessors is readily available from the factory.
相关PDF资料 |
PDF描述 |
|---|---|
| TLC541IFNRG3 | 11-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC20 |
| TLC541IN | 11-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP20 |
| TLC541IDWG4 | 11-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| TLC540IFNG3 | 11-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC20 |
| TLC540IDWR | 11-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TLC540IN | 功能描述:模数转换器 - ADC 8bit 11Chl A/D RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TLC540INE4 | 功能描述:模数转换器 - ADC 8Bit 75kSPS Serial Out On-Chip RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TLC541 | 制造商:TI 制造商全称:Texas Instruments 功能描述:8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS |
| TLC541I | 制造商:TI 制造商全称:Texas Instruments 功能描述:8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS |
| TLC541IDW | 功能描述:模数转换器 - ADC 8bit Serial Out RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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