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| 型号： | TLE4270D |
| 厂商： | Infineon Technologies |
| 文件页数： | 9/20页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 5V .55A DPAK-5 |
| 标准包装： | 2,500 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 5V |
| 输入电压： | 6 V ~ 42 V |
| 电压 - 压降（标准）： | 0.35V @ 550mA |
| 稳压器数量： | 1 |
| 电流 - 输出： | 550mA（最小值） |
| 电流 - 限制（最小）： | 650mA |
| 工作温度： | -40°C ~ 150°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-252-5，DPak（4 引线 + 接片），TO-252AD |
| 供应商设备封装： | P-TO252-5 |
| 包装： | 带卷 (TR) |
| 其它名称： | SP000012195 TLE4270DNT TLE4270DT |
TLE 4270
Design Notes for External Components
An input capacitor C I is necessary for compensation of line influences. The resonant
circuit consisting of lead inductance and input capacitance can be damped by a resistor
of approx. 1 ? in series with C I . An output capacitor C Q is necessary for the stability of
the regulating circuit. Stability is guaranteed at values of C Q ≥ 22 μ F and an ESR of
< 3 ? .
Reset Circuitry
If the output voltage decreases below 4.5 V, an external capacitor C D on pin 4 (D) will be
discharged by the reset generator. If the voltage on this capacitor drops below V DL , a
reset signal is generated on pin 2 (RO), i.e. reset output is set low. If the output voltage
rises above the reset threshold, C D will be charged with constant current. After the
power-on-reset time the voltage on the capacitor reaches V DU and the reset output will
be set high again. The value of the power-on-reset time can be set within a wide range
depending of the capacitance of C D .
Reset Timing
The power-on reset delay time is defined by the charging time of an external capacitor
C D which can be calculated as follows:
C D = ( ? t × I D,c )/ ? V
Definitions:
(1)
?
?
?
?
C D = delay capacitors
? t = reset delay time t rd
I D,c = charge current, typical 14 μ A
? V = V DU , typical 1.8 V
V DU = upper reset timing threshold at C D for reset delay time
t rd = ? V × C D / I D,c
(2)
The reset reaction time t rr is the time it takes the voltage regulator to set the reset out
LOW after the output voltage has dropped below the reset threshold. It is typically 1 μ s
for delay capacitor of 47 nF. For other values for C D the reaction time can be estimated
using the following equation:
t rr ≈ 20 s/F × C D
(3)
Data Sheet
9
Rev. 1.6, 2005-08-09
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