参数资料
型号: TLE4271S
厂商: INFINEON TECHNOLOGIES AG
元件分类: 固定正电压单路输出LDO稳压器
英文描述: 5 V FIXED POSITIVE LDO REGULATOR, 0.7 V DROPOUT, PSFM7
封装: PLASTIC, TO-220, 7 PIN
文件页数: 3/22页
文件大小: 164K
代理商: TLE4271S
TLE 4271
Data Sheet Rev. 2.1
11
2000-02-14
Application Description
The IC regulates an input voltage in the range of 5.5 V <
V
I <36Vto VQnom = 5.0 V. Up
to 26 V it produces a regulated output current of more than 550 mA. Above 26 V the
save-operating-area protection allows operation up to 36 V with a regulated output
current of more than 300 mA. Overvoltage protection limits operation at 42 V. The
overvoltage protection hysteresis restores operation if the input voltage has dropped
below 36 V. The IC can be switched off via the inhibit input, which causes the quiescent
current to drop below 50
A. A reset signal is generated for an output voltage of
V
Q < 4.5 V. The watchdog circuit monitors a connected controller. If there is no positive-
going edge at the watchdog input within a fixed time, the reset output is set to low. The
delay for power-on reset and the maximum permitted watchdog-pulse period can be set
externally with a capacitor.
Design Notes for External Components
An input capacitor
C
I is necessary for compensation of line influences. The resonant
circuit consisting of lead inductance and input capacitance can be damped by a resistor
of approx. 1
in series with C
I. An output capacitor CQ is necessary for the stability of
the regulating circuit. Stability is guaranteed at values of
C
Q ≥ 22 F and an ESR of
<3
.
Reset Circuitry
If the output voltage decreases below 4.5 V, an external capacitor
CD on pin D will be
discharged by the reset generator. If the voltage on this capacitor drops below
VDRL,a
reset signal is generated on pin RO, i.e. reset output is set low. If the output voltage rises
above the reset threshold,
CD will be charged with constant current. After the power-on-
reset time the voltage on the capacitor reaches
VDU and the reset output will be set high
again. The value of the power-on-reset time can be set within a wide range depending
of the capacitance of
CD.
Reset Timing
The power-on reset delay time is defined by the charging time of an external capacitor
Cd which can be calculated as follows:
Cd =(td × Id)/V
Definitions:
Cd = delay capacitor
td = reset delay time
Id = charge current, typical 5 mA
V = V
DU, typical 1.9 V
VDU = upper delay switching threshold at Cd for reset delay time
td = V × CD/ID
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