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参数资料
| 型号： | TLV1572CDR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封装： | GREEN, PLASTIC, SOIC-8 |
| 文件页数： | 2/15页 |
| 文件大小： | 348K |
| 代理商： | TLV1572CDR |
TLV1572
2.7 V TO 5.5 V, 10-BIT, 1.25 MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER WITH AUTO-POWERDOWN
SLAS171A – DECEMBER 1997– REVISED SEPTEMBER 1998
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
key points (continued)123
4.
Note that the device goes into autopower down on the 17th falling edge of SCLK (just after the LSB). The
FS rising edge pulls it out of autopower down. If FS comes on the 16th bit, the next conversion cycle starts
from the next rising edge allowing back to back conversions. An FS in the middle of a conversion cycle starts
a new conversion cycle. Thus variable-bit transfer is supported if FS appears earlier.
5.
DO goes into 3-state on the 17th rising edge and comes out on a FS rising edge.
6.
CS can be pulled high asynchronously to put the device into 3-state and powerdown. CS may also be pulled
low asynchronously to start checking for FS on the falling edges of the clock.
For applications where the analog input must be sampled at a precise instant in time, data conversion can be
initiated by an external conversion start pulse which is completely asynchronous to the SCLK as shown in Figure
4. When a conversion start pulse is received, the pulse is used as a frame sync (FS) signal to initiate the data
conversion and transfer. The corresponding timing diagram is shown in Figure 6.
interfacing TLV1572 to SPI/QSPI compatible microcontrollers (
Cs)
The TLV1572 is compatible with SPI and QSPI serial interface standards (Note: the TLV1572 supports the
following SPI clock options: clock_polarity= 0, i.e. SCLK idles low, and clock_phase = 1). Figure 7 shows the
pin connections to interface the TLV1572 to SPI/QSPI compatible microcontrollers.
CS
SCLK
FS
DO
XF
SCLK
DR
TLV1572
C
VCC
Figure 7. TLV1572 to
C Interface
1
2
3
45
67
16
0
MSB
SCLK
CS
FS
SDOUT
LSB
Figure 8. Typical Timing Diagram for
C Application
To use the TLV1572 in a non-DSP application, the FS input must be pulled high as shown in Figure 8.
A total of 16 clocks are normally supplied for each conversion. If the
C cannot take in 16 bits at a time, it may
take 8 bits with 8 clocks and next 8 bits with another 8 clocks. CS must be kept low throughout the conversion.
The delay between these two 8-clock periods must not be longer than 100
s.
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| TLV1572IDR | 功能描述:模数转换器 - ADC 10-Bit 1.25 MSPS 1-Ch DSP RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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