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参数资料
| 型号： | TLV2543CDWG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封装： | GREEN, PLASTIC, SOIC-20 |
| 文件页数： | 25/28页 |
| 文件大小： | 553K |
| 代理商： | TLV2543CDWG4 |
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TLV2543C, TLV2543I
12-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 ANALOG INPUTS
SLAS096C – MARCH 1995 – REVISED JUNE 2000
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
data output length (continued)
With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit
serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial-data stream
during the next I/O cycle. The current I/O cycle must be exactly 8 bits long to maintain synchronization, even
when this means corrupting the output data from the previous conversion. The four LSBs of the conversion
result are truncated and discarded. The current conversion is immediately started after the eighth falling edge
of the current I/O cycle.
Since D3 and D2 take effect on the current I/O cycle when the data length is programmed, there can be a conflict
with the previous cycle when the data-word length is changed from one cycle to the next. This may occur when
the data format is selected to be least significant bit first, since at the time the data length change becomes
effective (six rising edges of I/O CLOCK), the previous conversion result has already started shifting out.
In actual operation, when different data lengths are required within an application and the data length is changed
between two conversions, no more than one conversion result can be corrupted and only when it is shifted out
in LSB first format.
sampling period
During the sampling period, one of the analog inputs is internally connected to the capacitor array of the
converter to store the analog input signal. The converter starts sampling the selected input immediately after
the four address bits have been clocked into the input data register. Sampling starts on the fourth falling edge
of I/O CLOCK. The converter remains in the sampling mode until the eighth, twelfth, or sixteenth falling edge
of the I/O CLOCK depending on the data-length selection. After the EOC delay time from the last I/O CLOCK
falling edge, the EOC output goes low indicating that the sampling period is over and the conversion period has
begun. After EOC goes low, the analog input can be changed without affecting the conversion result. Since the
delay from the falling edge of the last I/O CLOCK to EOC low is fixed, time-varying analog input signals can be
digitized at a fixed rate without introducing systematic harmonic distortion or noise due to timing uncertainty.
After the 8-bit data stream has been clocked in, DATA INPUT should be held at a fixed digital level until EOC
goes high (indicating that the conversion is complete) to maximize the sampling accuracy and minimize the
influence of external digital noise.
data register, LSB first
D1 in the input data register (LSB first) controls the direction of the output binary data transfer. When D1 is set
to 0, the conversion result shifts out MSB first. When set to 1, the data shifts out LSB first. Selection of MSB
first or LSB first always affects the next I/O cycle and not the current I/O cycle. When changing from one data
direction to another, the current I/O cycle is never disrupted.
data register, bipolar format
D0 in the input data register controls the binary data format used to represent the conversion result. When D0
is set to 0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the conversion
result of an input voltage equal to Vref– is a code of all zeros (000 . . . 0), the conversion result of an input voltage
equal to Vref+ is a code of all ones (111 . . . 1), and the conversion result of (Vref + + Vref–)/2 is a code of a one
followed by zeros (100 ...0).
When D0 is set to 1, the conversion result is represented as bipolar data (signed binary). Nominally, conversion
of an input voltage equal to Vref– is a code of a 1 followed by zeros (100 . . . 0), conversion of an input voltage
equal to Vref+ is a code of a 0 followed by all ones (011 . . . 1), and the conversion of (Vref+ + Vref–)/2 is a code
of all zeros (000 . . . 0). The MSB is interpreted as the sign bit. The bipolar data format is related to the unipolar
format in that the MSBs are always each other’s complement.
Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output
during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the
current I/O cycle is not affected.
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