- 您现在的位置：买卖IC网 > PDF目录98252 > TLV2553IDWRG4 (TEXAS INSTRUMENTS INC) 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 PDF资料下载
参数资料
| 型号： | TLV2553IDWRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封装： | GREEN, PLASTIC, SOIC-20 |
| 文件页数： | 16/29页 |
| 文件大小： | 603K |
| 代理商： | TLV2553IDWRG4 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页当前第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页
TLV2553
SLAS354B – SEPTEMBER 2001 – REVISED SEPTEMBER 2002
23
www.ti.com
PRINCIPLES OF OPERATION
data output length (continued)
With bits D3 and D2 set to 01, the 8-bit data-length mode is selected, which allows fast communication with 8-bit
serial interfaces. In the 8-bit mode, the result of the current conversion is output as an 8-bit serial data stream
during the next I/O cycle. The current I/O cycle must be exactly eight bits long to maintain synchronization, even
when this means corrupting the output data from the previous conversion. The four LSBs of the conversion
result are truncated and discarded. The current conversion is started immediately after the eighth falling edge
of the current I/O cycle.
Since the D3 and D2 register settings take effect on the I/O cycle when the data length is programmed, there
can be a conflict with the previous cycle if the data-word length was changed. This may occur when the data
format is selected to be least significant bit first, since at the time the data length change becomes effective (six
rising edges of I/O CLOCK), the previous conversion result has already started shifting out. In actual operation,
when different data lengths are required within an application and the data length is changed between two
conversions, no more than one conversion result can be corrupted and only when it is shifted out in LSB-first
format.
LSB out first
D1 in the CFGR1 controls the direction of the output (binary) data transfer. When D1 is reset to 0, the conversion
result is shifted out MSB first. When set to 1, the data is shifted out LSB first. Selection of MSB first or LSB first
always affects the next I/O cycle and not the current I/O cycle. When changing from one data direction to
another, the current I/O cycle is never disrupted.
bipolar output format
D0 in the CFGR1 controls the binary data format used to represent the conversion result. When D0 is cleared
to 0, the conversion result is represented as unipolar (unsigned binary) data. Nominally, the conversion result
of an input voltage equal to or less than VREF– is a code with all zeros (000 . . . 0) and the conversion result of
an input voltage equal to or greater than VREF+ is a code of all ones (111 . . . 1). The conversion result of (VREF+
+ VREF–)/2 is a code of a one followed by zeros (100 ...0).
When D0 is set to 1, the conversion result is represented as bipolar (signed binary) data. Nominally, conversion
of an input voltage equal to or less than VREF– is a code of a one followed by zeros (100 . . . 0), and the conversion
of an input voltage equal to or greater than VREF+ is a code of a zero followed by all ones
(011 . . . 1). The conversion result of (VREF+ + VREF–)/2 is a code of all zeros (000 . . . 0). The MSB is interpreted
as the sign bit. The bipolar data format is related to the unipolar format in that the MSBs are always each other’s
complement.
Selection of the unipolar or bipolar format always affects the current conversion cycle, and the result is output
during the next I/O cycle. When changing between unipolar and bipolar formats, the data output during the
current I/O cycle is not affected.
reference
An external reference can be used through two reference input pins, REF+ and REF–. The voltage levels
applied to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and
zero-scale reading respectively. The values of REF+, REF–, and the analog input should not exceed the positive
supply or be lower than GND consistent with the specified absolute maximum ratings. The digital output is at
full scale when the input signal is equal to or higher than REF+ and at zero when the input signal is equal to or
lower than REF–.
相关PDF资料 |
PDF描述 |
|---|---|
| TLV2553IPWRG4 | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| TLV2553IDW | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| TLV2553IPWG4 | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| TLV2553IPW | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| TLV2553IDWR | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TLV2553IDWRQ1 | 功能描述:模数转换器 - ADC Auto Cat 12B 200KSPS 11Ch Low-Pwr Ser ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TLV2553IPW | 功能描述:模数转换器 - ADC 12-Bit 200 KSPS 11 Ch Lo-Pwr RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TLV2553IPWG4 | 功能描述:模数转换器 - ADC 12-Bit 200 KSPS 11 Ch Lo-Pwr RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TLV2553IPWR | 功能描述:模数转换器 - ADC 12-Bit 200 KSPS 11 Ch Lo-Pwr RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TLV2553IPWRG4 | 功能描述:模数转换器 - ADC 12-Bit 200 KSPS 11 Ch Lo-Pwr RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
发布紧急采购，3分钟左右您将得到回复。