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参数资料
| 型号： | TLV2556IDWR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 11-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封装： | GREEN, PLASTIC, SOIC-20 |
| 文件页数： | 25/37页 |
| 文件大小： | 729K |
| 代理商： | TLV2556IDWR |
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TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
31
www.ti.com
PRINCIPLES OF OPERATION
C1
0.1
F
Decoupling Cap
C2
10
F
Int Reference
Compensation Cap
GND
Analog
Supply
Sample
50 pF
CDAC
Convert
REF+
REF–
Internal
Reference
VCC
S1, S2:
Closed = Internal Reference Used
Opened = External Reference Used
C2 and Grounding REF– Are Required
When Either 4.096 V or 2.048 Internal
Reference Is Used
S1
S2
Figure 54. Reference Block
INT/EOC output
Pin 19 outputs the status of the ADC conversion. When programmed as EOC, the output indicates the beginning
and the end of conversion. In the reset state, EOC is always high. During the sampling period (beginning after
the fourth falling edge of the I/O CLOCK sequence), EOC remains high until the internal sampling switch of the
converter is safely opened. The opening of the sampling switch occurs after the eighth, twelfth, or sixteenth I/O
CLOCK falling edge, depending on the data-length selection in the input data register. After the EOC signal goes
low, the analog input signal can be changed without affecting the conversion result.
The EOC signal goes high again after the conversion is completed and the conversion result is latched into the
output data register. The rising edge of EOC returns the converter to a reset state and a new I/O cycle begins.
On the rising edge of EOC, the first bit of the current conversion result is on DATA OUT when CS is low. When
CS is toggled between conversions, the first bit of the current conversion result occurs on DATA OUT at the
falling edge of CS.
When programmed as INT, the output indicates that the conversion is completed and the output data is ready
to be read. In the reset state, INT is always high. INT is high during the sampling period and until the conversion
is complete. After the conversion is finished and the output data is latched, INT goes low and remains low until
it is cleared by the host. When CS is held low, the MSB (or LSB) of the conversion result is presented on DATA
OUT on the falling edge of INT. A rising I/O CLOCK edge clears the interrupt.
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| TLV2556IDWRG4 | 功能描述:模数转换器 - ADC 12B 200 KSPS 11Ch Lo Pwr Serial ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TLV2556IPW | 功能描述:模数转换器 - ADC 12-Bit 200 KSPS 11 Ch Lo-Pwr RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TLV2556IPW | 制造商:Texas Instruments 功能描述:12BIT ADC 200KSPS 2556 TSSOP20 制造商:Texas Instruments 功能描述:12BIT ADC, 200KSPS, 2556, TSSOP20 制造商:Texas Instruments 功能描述:12BIT ADC, 200KSPS, 2556, TSSOP20; Resolution (Bits):12bit; Sampling Rate:200kSPS; Supply Voltage Type:Single; Supply Voltage Min:2.7V; Supply Voltage Max:5.5V; Supply Current:3mA; Digital IC Case Style:TSSOP; No. of Pins:20; Input ;RoHS Compliant: Yes |
| TLV2556IPWG4 | 功能描述:模数转换器 - ADC 12-Bit 200 KSPS 11 Ch Lo-Pwr RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TLV2556IPWR | 功能描述:模数转换器 - ADC 12-Bit 200 KSPS 11 Ch Lo-Pwr RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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