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参数资料
| 型号： | TLV320AIC14C |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO30 |
| 封装： | PLASTIC, TSSOP-30 |
| 文件页数： | 6/54页 |
| 文件大小： | 450K |
| 代理商： | TLV320AIC14C |
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3–1
3 Functional Description
3.1
Operating Frequencies (see Notes)
The sampling frequency is the frequency of the frame sync (FS) signal whose falling edge starts digital-data transfer
for both ADC and DAC. The sampling frequency is derived from the master clock (MCLK) input by the following
equations:
Coarse sampling frequency (default):
The coarse sampling is selected by programming P = 8 in the control register 4, which is the default
configuration of AIC14 on power-up or reset.
FS = Sampling (conversion) frequency = MCLK / (16
× M × N x 8)
Fine sampling frequency (see Note 5):
FS = Sampling (conversion) frequency = MCLK/ (16
× M × N × P)
NOTES:
1. Use control register 4 to set the following values of M, N, and P
2. M = 1,2, . . . ,128
3. N = 1,2, . . . ,16
4. P = 1,2, . . . ,8
5. The fine sampling rate needs an on-chip DLL to generate internal clocks. The DLL requires the relationship
between MCLK and P to meet the following condition: 10 MHz
≤ (MCLK/P) ≤ 25 MHz
6. Both equations of FS require that the following conditions should be met:
S (M × N × P) ≥ (devnum × mode) if the FIR/IIR filter is not bypassed.
S [Integer(M/4) × N × P] ≥ (devnum × mode) if the FIR/IIR filter is bypassed.
where
devnum is the number of devices connecting in cascade
mode is equal to 1 for continuous data transfer mode and 2 for programming mode
EXAMPLE:
The MCLK comes from the DSP C5402’s CLKOUT and equals to 20.48 MHz and the conversion rate of 8 kHz is
desired. First, set P = 1 to satisfy the condition 5 so that (MCLK/P) = 20.48 MHz/1 = 20.48 MHz. Next, pick
M = 10 and N = 16 to satisfy condition 6 and derive 8 kHz for FS. That is,
FS = 20.48 MHz/ (16
× 10 × 16 × 1) = 8 kHz
3.2
Internal Architecture
3.2.1
Antialiasing Filter
The built-in antialiasing filter is a two-pole filter that has a 20-dB attenuation at 1 MHz.
3.2.2
Sigma-Delta ADC
The sigma-delta analog-to-digital converter is a sigma-delta modulator with 128-x oversampling. The ADC provides
high-resolution, low-noise performance using oversampling techniques. Due to the oversampling employed, only
single pole R-C filters are required on the analog inputs.
3.2.3
Decimation Filter
The decimation filters are either FIR filters or IIR filters, selected by bit D5 of the control register 1. The FIR filter
provides linear-phase output with 17/f group delay, whereas the IIR filter generates nonlinear phase output with
negligible group delay. The decimation filters reduce the digital data rate to the sampling rate. This is accomplished
by decimating with a ratio of 1:128. The output of the decimation filter is a 16-bit 2s-complement data word clocking
at the sample rate selected for that particular data channel. The BW of the filter is (0.45
× FS) and scales linearly with
the sample rate.
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