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| 型号： | TLV320AIC20KIPFBRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封装： | GREEN, PLASTIC, TQFP-48 |
| 文件页数： | 18/52页 |
| 文件大小： | 981K |
| 代理商： | TLV320AIC20KIPFBRG4 |
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Power Management
Smart Time Division Multiplexed Serial Port (SMARTDM)
TLV320AIC20, TLV320AIC21
TLV320AIC24, TLV320AIC25
TLV320AIC20K, TLV320AIC24K
SLAS363D – MARCH 2002 – REVISED APRIL 2005
Functional Description (continued)
The Master device always has its FS configured as an output and the last slave in the cascade (i.e. channel with
address 0) always has its FSD configured as an input.
To calculate the channel address, during the first 64 MCLKs, the device counts the number of clocks between
ACD starting (reset) and the FSD going high.
During the next 64 MCLKs, the device counts the number of clocks till FS is pulled low.
The sum total of the counts in the first phase and the second phase is the number of devices in the channel.
For a cascaded system the rise time of H/W RESET must be less than the MCLK period and should satisfy setup
time requirement of 2 ns with respect to MCLK rise-edge. If more than one codec is cascaded together, RESET
must be synchronized to MCLK. Additionally all devices must see the same edge of MCLK within a window of 0.5
ns. This requirement does not exist for a single master or slave. MCLK and RESET can be asynchronous
events.
Most of the device (all except the digital interface) enters the power-down mode when D5 and D4, in control
register 3A, are set to 1. When the PWRDN pin is low, the entire device is powered down. In either case, register
contents are preserved and the output of the amplifier is held at midpoint voltage to minimize pops and clicks.
The amount of power drawn during software power down is higher than during a hardware power down because
of the current required to keep the digital interface active. Additional differences between software and hardware
power-down modes are detailed in the following paragraphs.
Software Power-Down
Data bits D5 and D4 of control register 3A are used by TLV320AIC2x to turn on or off the software power-down
mode, which takes effect in the next frame FS. The ADC and DAC can be powered down individually. In the
software power-down, the digital interface circuit is still active while the internal ADC and DAC channel and all
differential analog outputs are disabled, and DOUT is put in 3-state in the data frame only. Register data in the
control frame is still accepted via DIN, but data in the data frame is ignored. The device returns to normal
operation when D7 and D6 of control register 3A are reset.
If the PLL is enabled (i.e., P is not set to 8), then executing a software power down and power up of the device
causes the output drivers to go to the common-mode voltage. Therefore, before executing a software power
down, the PLL must first be disabled (i.e., P should first be set to 8) before control register 3A is programmed.
While bringing the codec out of software power down, the PLL should be re-enabled only after the codec is
brought out of power down (i.e., register 3A must be programmed first followed by register 4).
Hardware Power-Down
The TLV320AIC2x requires the PWRDN signal to be synchronized with MCLK. When PWRDN is held low, the
device enters hardware power-down mode. In this state, the internal clock control circuit and the differential
outputs are disabled. All other digital I/Os are disabled and DIN can not accept any data input. The device can
only be returned to normal operation by holding PWRDN high. When not holding the device in the hardware
power-down mode, PWRDN must be tied high.
The SMART time division multiplexed serial port (SMARTDM) uses the four wires of DOUT, DIN, SCLK, and FS
to transfer data into and out of the AIC2x. The TLV320AIC2xs SMARTDM supports three serial interface
configurations (see Table 1): stand-alone master, stand-alone slave, and master-slave cascade, employing a
time division multiplexed (TDM) scheme (a cascade of only-slaves is not supported). The SMARTDM allows for a
serial connection of up to 8 stereo codecs to a single serial port. Data communication in the three serial interface
configurations can be carried out in either standard operation (Default) or turbo operation. Each operation has
two modes: programming mode (default mode) and continuous data transfer mode. To switch from the
programming mode to the continuous data transfer mode, set bit D6 of control register 1 to 1, which is reset
automatically after switching back to programming mode. The TLV320AIC2x can be switched back from the
continuous data transfer mode to the programming mode by setting the LSB of the data on DIN to 1, only if the
data format is (15+1), as selected by bit 0 of control register 1. The SMARTDM automatically adjusts the number
25
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TLV320AIC21 | 制造商:TI 制造商全称:Texas Instruments 功能描述:Layout and Grounding Guidelines for TLV320AIC2x |
| TLV320AIC21C | 制造商:TI 制造商全称:Texas Instruments 功能描述:Layout and Grounding Guidelines for TLV320AIC2x |
| TLV320AIC21CPFB | 功能描述:接口—CODEC Low Power Low IOVdd Dual Channel RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| TLV320AIC21CPFBG4 | 功能描述:接口—CODEC 64 x 18 3.3-V Synch FIFO Memory RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| TLV320AIC21CPFBR | 功能描述:接口—CODEC Low Power Low IOVdd Dual Channel RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
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