参数资料
型号: TLV320AIC23EVM2
厂商: Texas Instruments
文件页数: 35/47页
文件大小: 0K
描述: EVAL MOD FOR TLV320AIC23/DAC23
标准包装: 1
主要目的: 音频编解码器
嵌入式:
已用 IC / 零件: TLV320AIC23
主要属性: 立体声 16 ~ 32 位 8 ~ 96 kHz 采样率
次要属性: 图形用户界面,90dB SNR 模数转换器和 100dB SNR 数模转换器,I2C 和 SPI 接口
已供物品:
配用: WM2582-ND - EVALDI EARBUDS TYPE Y
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TLV320AIC23PWR-ND - IC AUDIO CODEC 32BIT SER 28TSSOP
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TLV320AIC23IGQE-ND - IC AUDIO CODEC 32BIT SER 80BGA
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Chapter 5
I 2 C Error Messages
The error messages are only visible during error conditions. The error
messages are located just above the RESET button in the main panel. The first
message to appear will be above the second message. For example, if an ACK
error occurs first then it is displayed first and it is only displayed once. The
software continues to send data to the device even with ACK and WAIT errors.
But it no longer looks for ACK or WAIT errors, therefore the response from the
device can be undetermined.
No.
1
2
Error Message
ACK error
WAIT error
Cause
The AIC23/DAC23 is not sending an acknowledge command back to the host processor.
This is referred to as an ACK in I 2 C terminology. The software does not terminate the
transactions.
Pin 1 (SDA) or pin 14 (SCL) on the parallel cable is not allowing the I 2 C commands to
reach the EVM.
Pin 15 on the parallel cable is not allowing the ACK command to return back to the host.
The LPT port is not connected and configured for EPP or bidirectional mode (PS-2 in
some cases).
The actual LPT port connected does not match the LPT port selected in the *.dat file.
LPT1 is the default for the LPT port, if it is not explicitly defined in the file. The
hexadecimal addresses for the ports defined in the software are LPT1 = 0x378,
LPT2 = 0x278, and LPT3 = 0x3BC.
The actual LPT port base address selected does not match any of the following
hexadecimal addresses:
LPT1 = 0x378
LPT2 = 0x278
LPT3 = 0x3BC
The AIC23/DAC23 is holding the SCL line low and not releasing it for the host processor.
This is referred to as waiting the bus in I 2 C terminology. The AIC23/DAC23 software
does not terminate the transactions.
Pin 1 (SDA) or pin 14 (SCL) on the parallel cable is not allowing the I 2 C commands to
reach the EVM.
Pin 10 on the parallel cable is not allowing the host to read a high SCL. Therefore a WAIT
is assumed.
I 2 C Error Messages
5-1
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