- 您现在的位置：买卖IC网 > PDF目录297500 > TLV320AIC26IRHBG4 (Texas Instruments, Inc.) LOW POWER STEREO AUDIO CODEC WITH HEADPHONE/SPEAKER AMPLIFIER AND 12-BIT BATTERY / TEMPERATURE / AUXILIARY ADC PDF资料下载
参数资料
| 型号： | TLV320AIC26IRHBG4 |
| 厂商： | Texas Instruments, Inc. |
| 元件分类： | Codec |
| 英文描述： | LOW POWER STEREO AUDIO CODEC WITH HEADPHONE/SPEAKER AMPLIFIER AND 12-BIT BATTERY / TEMPERATURE / AUXILIARY ADC |
| 中文描述： | 低功耗立体声音频编解码器耳机/扬声器放大器和12位电池/温度/辅助ADC |
| 文件页数： | 11/74页 |
| 文件大小： | 896K |
| 代理商： | TLV320AIC26IRHBG4 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页当前第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页
TLV320AIC26
SLAS412 DECEMBER 2003
www.ti.com
19
AUDIO DATA CONVERTERS
The ’AIC26 has a stereo audio DAC and a mono audio ADC. Both ADC and DAC can operate with a maximum sampling
rate of 53 kHz and support all audio standard rates of 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz,
44.1 kHz, and 48 kHz. By utilizing the flexible clock generation capability and internal programmable interpolation, a wide
variety of sampling rates up to 53 kHz can be obtained from many possible MCLK inputs. In addition, the DAC and ADC
can independently operate at different sampling rates as indicated in control register REG00H/Page2.
When the ADC or DAC is operating, the ’AIC26 requires an applied audio MCLK input. The user should also set
bit D13/REG06H/Page2 to indicate which Fsref rate is being used. If the codec ADC or DAC is powered up, then the
auxiliary ADC uses MCLK and BCLK for its internal clocking, and the internal oscillator is powered down to save power.
Typical audio DACs can suffer from poor out-of-band noise performance when operated at low sampling rates, such as
8 kHz or 11.025 kHz. The ’AIC26 includes programmable interpolation circuitry to provide improved audio performance at
such low sampling rates, by first upsampling low-rate data to a higher rate, filtering to reduce audible images, and then
passing the data to the internal DAC, which is actually operating at the Fsref rate. This programmable interpolation is
determined using bit D5D3/REG00H/Page2.
For example, if playback of 11.025-kHz data is required, the ’AIC26 can be configured such that Fsref = 44.1 kHz. Then
using bit D5D3/REG00H/Page2, the DAC sampling rate (Fs) can be set to Fsref/4, or Fs = 11.025 kHz. In operation, the
11.025-kHz digital input data is received by the ’AIC26, upsampled to 44.1 kHz, and filtered for images. It is then provided
to the audio DAC operating at 44.1 kHz for playback. In reality, the audio DAC further upsamples the 44.1 kHz data by a
ratio of 128x and performs extensive interpolation filtering and processing on this data before conversion to a stereo analog
output signal.
PLL
The ’AIC26 has an on-chip PLL to generate the needed internal ADC and DAC operational clocks from a wide variety of
clocks available in the system. The PLL supports an MCLK varying from 2 MHz to 50 MHz and is register programmable
to enable generation of required sampling rates with fine precision.
ADC and DAC sampling rates are given by
DAC_FS = Fsref/N1 and ADC_FS = Fsref/N2
where, Fsref must fall between 39 kHz and 53 kHz, and N1, N2 =1, 1.5, 2, 3, 4, 5, 5.5, 6 are register programmable.
The PLL can be enabled or disabled using register programming.
D When PLL is disabled
Fsref
+ MCLK
128
Q
Q = 2, 3
…17
Note: For ADC, with N2 = 1.5 or 5.5, odd values of Q are not allowed.
In this mode, the MCLK can operate up to 50 MHz, and Fsref should fall within 39 kHz to 53 kHz.
D When PLL is enabled
Fsref
+ MCLK
K
2048
P
P = 1, 2, 3,
…, 8
K = J.D
J = 1, 2, 3,
….,64
D = 0, 1, 2,
…, 9999
P, J, and D are register programmable, where J is an integer part of K before the decimal point, and D is a four-digit fractional
part of K after the decimal point, including lagging zeros.
Examples:
If K = 8.5, Then J = 8, D = 5000
If K = 7.12, Then J = 7, D = 1200
If K = 7.012, Then J = 7, D = 120
The PLL is programmed through Registers 1BH and 1CH of Page2.
相关PDF资料 |
PDF描述 |
|---|---|
| TLV320AIC26IRHBR | LOW POWER STEREO AUDIO CODEC WITH HEADPHONE/SPEAKER AMPLIFIER AND 12-BIT BATTERY / TEMPERATURE / AUXILIARY ADC |
| TLV320AIC26IRHB | LOW POWER STEREO AUDIO CODEC WITH HEADPHONE/SPEAKER AMPLIFIER AND 12-BIT BATTERY / TEMPERATURE / AUXILIARY ADC |
| TLV320AIC29_07 | STWREO AUDIO CODEC WITH INTERGRATED HEADPHONE AND SPEAKER AMPLIFIERS |
| TLW-102-06-G-D-01 | 4 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, SOLDER |
| TM16EN72LPU-40 | 16M X 72 EDO DRAM MODULE, 20 ns, DMA168 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TLV320AIC26IRHBR | 功能描述:接口—CODEC Lo-Pwr Stereo Codec RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| TLV320AIC26IRHBRG4 | 功能描述:接口—CODEC Lo-Pwr Stereo Codec RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| TLV320AIC27 | 制造商:TI 制造商全称:Texas Instruments 功能描述:STEREO AUDIO CODEC |
| TLV320AIC27CPFB | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TLV320AIC27IPFB | 制造商:TI 制造商全称:Texas Instruments 功能描述:STEREO AUDIO CODEC |
发布紧急采购，3分钟左右您将得到回复。