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参数资料
| 型号： | TLV320AIC27TPFB |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封装： | PLASTIC, TQFP-48 |
| 文件页数： | 16/54页 |
| 文件大小： | 732K |
| 代理商： | TLV320AIC27TPFB |
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TLV320AIC27
STEREO AUDIO CODEC
SLAS253A – MARCH 2000 – REVISED SEPTEMBER 2000
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
slot 12: GPIO control
Data in this slot is applied to the GPIO pins if they have been enabled via the control registers. Note that only
bits 11, 12, and 13 are supported and all others are ignored.
ac-link audio input frame (SDATA_IN)
SYNC
BIT_CLK
SDATA_IN
CODEC
READY
SLOT(1)
SLOT(2)
SLOT(12)
’0’
19
0
19
0
19
0
19
0
12.288 MHz
81.4 nS
END OF PREVIOUS
AUDIO FRAME
TIME SLOT ’VALID’ BITS
(’1’ = TIME SLOT CONTAINS
VALID PCM DATA)
SLOT (1)
SLOT (2)
SLOT (3)
SLOT (12)
DATA PHASE
TAG PHASE
20.8
S (48 kHz)
Figure 11. AC-Link Audio Input Frame
The audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the
AC’97 controller. As in the case of audio output frame, each ac-link audio input frame consists of 12 20-bit time
slots.
Slot 0 is a specially reserved time slot containing 16 bits, which are used for ac-link protocol infrastructure. The
first bit in slot 0 is a global bit (SDATA_IN, bit 15) which flags whether the TLV320AIC27 is in the codec-ready
state or not. A codec-ready bit equal to 0 indicates that the TLV320AIC27 is not ready for normal operation. For
example, this is a normal condition following reset, while the TLV320AIC27’s voltage references settle. An
ac-link codec-ready indicator bit equal to 1 indicates that the ac link and the TLV320AIC27 control and status
registers are in fully-operational state. The AC’97 controller must further probe the power-down control/status
register to determine exactly which subsections, if any, are ready.
Prior to any attempts at putting the TLV320AIC27 into operation, the AC’97 controller should poll the first bit in
the audio input frame (SDATA_IN slot 0, bit 15) for an indication that the TLV320AIC27 is codec-ready.
Once the TLV320AIC27 is codec-ready, the next 12 bit positions sampled by the AC’97 controller indicate which
of the corresponding 12 time slots are assigned to input data streams and contain valid data. Figure 11 illustrates
the time-slot-based ac-link protocol.
There are several subsections within the TLV320AIC27 that can independently go busy/ready. It is the
responsibility of the TLV320AIC27 controller to probe more deeply into the TLV320AIC27 register file to
determine which of the TLV320AIC27 subsections are actually ready.
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