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参数资料
| 型号： | TLV320AIC3253IRGER |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC24 |
| 封装： | 4 X 4 MM, PLASTIC, QFN-24 |
| 文件页数： | 17/35页 |
| 文件大小： | 738K |
| 代理商： | TLV320AIC3253IRGER |
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SLOS631 – MARCH 2010
www.ti.com
The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master mode,
this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in Page 0,
Register 30 (see ). The number of bit-clock pulses in a frame may need adjustment to accommodate various
word-lengths as well as to support the case when multiple TLV320AIC3253s may share the same audio bus.
The TLV320AIC3253 also includes a feature to offset the position of start of data transfer with respect to the
word-clock. This offset can be controlled in terms of number of bit-clocks and can be programmed in Page 0,
Register 28.
The TLV320AIC3253 also has the feature of inverting the polarity of the bit-clock used for transferring the audio
data as compared to the default clock polarity used. This feature can be used independently of the mode of
audio interface chosen. This can be configured via Page 0, Register 29, D(3).
The TLV320AIC3253 further includes programmability (Page 0, Register 27, D0) to place the DOUT line into a
hi-Z (3-state) condition during all bit clocks when valid data is not being sent. By combining this capability with
the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be
accomplished, enabling the use of multiple codecs on a single audio serial data bus. When the audio serial data
bus is powered down while configured in master mode, the pins associated with the interface are put into a hi-Z
output condition.
By default when the word-clocks and bit-clocks are generated by the TLV320AIC3253, these clocks are active
only when the codec (ADC, DAC or both) are powered up within the device. This is done to save power.
However, it also supports a feature when both the word clocks and bit-clocks can be active even when the codec
in the device is powered down. This is useful when using the TDM mode with multiple codecs on the same bus,
or when word-clock or bit-clocks are used in the system as general-purpose clocks.
Clock Generation and PLL
The TLV320AIC3253 supports a wide range of options for generating clocks for the ADC and DAC sections as
well as interface and other control blocks. The clocks for ADC and DAC require a source reference clock. This
clock can be provided on variety of device pins such as MCLK, BCLK or GPI pins. The CODEC_CLKIN can then
be routed through highly-flexible clock dividers to generate the various clocks required for ADC, DAC and the
miniDSP sections. In the event that the desired audio or miniDSP clocks cannot be generated from the reference
clocks on MCLK BCLK or GPIO, the TLV320AIC3253 also provides the option of using the on-chip PLL which
supports a wide range of fractional multiplication values to generate the required clocks. Starting from
CODEC_CLKIN the TLV320AIC3253 provides several programmable clock dividers to help achieve a variety of
sampling rates for ADC, DAC and clocks for the miniDSP .
For more detailed information see the Application Reference Guide, SLAU303
Control Interfaces
The TLV320AIC3253 control interface supports SPI or I2C communication protocols, with the protocol selectable
using the SPI_SELECT pin. For SPI, SPI_SELECT should be tied high; for I2C, SPI_SELECT should be tied low.
It is not recommended to change the state of SPI_SELECT during device operation.
I2C Control
The TLV320AIC3253 supports the I2C control protocol, and will respond to the I2C address of 0011000. I2C is a
two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus
only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the
bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW.
This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.
SPI Control
In the SPI control mode, the TLV320AIC3253 uses the pins SCL/SSZ=SSZ, SCLK=SCLK, MISO=MISO,
SDA/MOSI=MOSI as a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit
CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the
master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the
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Copyright 2010, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC3253
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相关代理商/技术参数 |
参数描述 |
|---|---|
| TLV320AIC3253IRGET | 功能描述:接口—CODEC Ultra Low Pwr Stereo Audio Codec RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| TLV320AIC3253IYZKR | 功能描述:接口—CODEC Ultra Low Pwr Stereo Audio Codec RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| TLV320AIC3253IYZKT | 功能描述:接口—CODEC Ultra Low Pwr Stereo Audio Codec RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| TLV320AIC3254 | 制造商:TI 制造商全称:Texas Instruments 功能描述:Ultra Low Power Stereo Audio Codec With Embedded miniDSP |
| TLV320AIC3254_09 | 制造商:TI 制造商全称:Texas Instruments 功能描述:Ultra Low Power Stereo Audio Codec With Embedded miniDSP |
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