参数资料
型号: TLV5580IDWRG4
厂商: TEXAS INSTRUMENTS INC
元件分类: ADC
英文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封装: GREEN, PLASTIC, SOIC-28
文件页数: 10/35页
文件大小: 451K
代理商: TLV5580IDWRG4
TLV5580
8BIT, 80 MSPS LOW POWER A/D CONVERTER
SLAS205B DECEMBER 1998 REVISED OCTOBER 2003
www.ti.com
18
TLV5580 EVALUATION MODULE
TI provides an evaluation module (EVM) for TLV5580. The EVM also includes a 10-bit 80 MSPS DAC so that
the user can convert the digitized signal back to the analog domain for functional testing. Performance
measurements can be done by capturing the ADC’s output data.
The EVM provides the following additional features:
D Provision of footprint for the connection of an onboard crystal oscillator, instead of using an external clock input.
D Use of TLV5580 internal or external voltage references. In the case of external references, an onboard circuit
is used that derives adjustable bottom and top reference voltages from a bandgap reference. Two potentiometers
allow for the independent adjustments of both references. The full scale ADC range can be adjusted to the input
signal amplitude.
D All digital output, control signal I/O (output enable, standby, reference power-down) and clock I/O are provided
on a single connector. The EVM can thus be part of a larger (DSP) system for prototyping.
D Onboard prototyping area with analog and digital supply and ground connections.
Figure 15 shows the EVM schematic.
The EVM is factory shipped for use in the following configuration:
D Use of external (onboard) voltage references
D External clock input
ANALOG INPUT
A signal in the range between V(REFBI) and V(REFTI) should be applied to avoid overflow/underflow on connector
J10. This signal is onboard terminated with 50
. There is no onboard biasing of the signal. When using external
(onboard) references, these levels can be adjusted with R7 (V(REFTI)) and R6 (V(REFBI)). Adjusting R7 causes
both references to shift. R6 only impacts the bottom reference. The range of these signals for which the device
is specified depends on AVDD and is shown under the Recommended Operating Conditions.
Internally generated reference levels are also dependent on AVDD as shown in the electrical characteristics
section.
CLOCK INPUT
A clock signal should be applied with amplitudes ranging from 0 to AVDD with a frequency equal to the desired
sampling frequency on connector J9. This signal is onboard terminated with 50
. Both ADC and DAC run off
the same clock signal. Alternatively the clock can be applied from terminal 1 on connector J11. A third option
is using a crystal oscillator. The EVM board provides the footprint for a crystal oscillator that can be populated
by the end-user, depending on the desired frequency. The footprint is compatible with the Epson EG-8002DC
series of programmable high-frequency crystal oscillators. Refer to the TLV5580 EVM Settings for selecting
between the different clock modes.
相关PDF资料
PDF描述
TLV5580CDW 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV5580CPW 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV5580IDW 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV5580CDWR 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
TLV5580CPWR 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
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