参数资料
型号: TLV5610IYER
厂商: TEXAS INSTRUMENTS INC
元件分类: DAC
英文描述: SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, PBGA20
封装: WAFER CHIP SCALE, 20 PIN
文件页数: 5/17页
文件大小: 345K
代理商: TLV5610IYER
TLV5610IYE
TLV5608IYE
SLAS393 OCTOBER 2003
www.ti.com
13
USING TLV5610IYE AND TLV5608IYE, WAFER CHIP SCALE PACKAGE (WCS)
D TLV5610 and TLV5608 qualifications were done using a wire-bonded small outline (SOIC) package and
includes: steady state life, thermal shock, ESD, latch-up, biased HAST, autoclave, and characterization.
These qualified devices are orderable as TLV5610IDW and TLV5608IDW.
D The wafer chip-scale package (WCS), TLV5610IYE and TLV5608IYE, uses the same DIE as
TLV5610IDW and TLV5608IDW respectively, but are not qualified. WCS qualification, including board
level reliability (BLR), is the responsibility of the customer.
D It is recommended that underfill be used for increased reliability. BLR is application dependent, but may
include test such as: temperature cycling, drop test, key push, bend, vibration, and package shear.
The following WCSP information provides the user of the TLV5610IYE and TLV5608IYE with some general
guidelines for board assembly.
D Melting point of eutectic solder is 183°C.
D Recommended peak reflow temperatures are in the 220°C to 230°C range.
D The use of underfill is required. The use of underfill greatly reduces the risk of thermal mismatch fails.
Underfill is an epoxy/adhesive that may be added during the board assembly process to improve board
level/system level reliability. The process is to dispense the epoxy under the dice after die attach reflow. The
epoxy adheres to the body of the device and to the printed-circuit board. It reduces stress placed upon the solder
joints due to the thermal coefficient of expansion (TCE) mismatch between the board and the component.
Underfill material is highly filled with silica or other fillers to increase an epoxy’s modulus, reduce creep
sensitivity, and decrease the material’s TCE.
The recommendation for peak flow temperatures of 220
°C to 230°C is based on general empirical results that
indicate that this temperature range is needed to facilitate good wetting of the solder bump to the substrate or
circuit board pad. Lower peak temperatures may cause nonwets (cold solder joints).
Bottom View
Top View
NOTES:A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
Figure 11. TLV5610IYE and TLV5608IYE Wafer Chip Scale Package
相关PDF资料
PDF描述
TLV5610IYZT SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, BGA20
TLV5610IYZR SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, BGA20
TLV5610IYZ SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, BGA20
TLV5613CDWRG4 PARALLEL, WORD INPUT LOADING, 1 us SETTLING TIME, 12-BIT DAC, PDSO20
TLV5613IDW PARALLEL, WORD INPUT LOADING, 1 us SETTLING TIME, 12-BIT DAC, PDSO20
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