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参数资料
| 型号： | TLV5610IYZR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, BGA20 |
| 封装： | GREEN, WCSP-20 |
| 文件页数： | 2/14页 |
| 文件大小： | 180K |
| 代理商： | TLV5610IYZR |
www.ti.com
DAC A-H AND TWO-CHANNEL REGISTERS
PRESET
CTRL0
CTRL1
SBAS389A – JULY 2006 – REVISED JULY 2006
Writing to DAC A–H sets the output voltage of channel A–H. It is possible to automatically generate the
complement of one channel by writing to one of the four, two-channel registers (DAC A and B, etc.).
The TLV5610IYZ decodes all 12 data bits.
The outputs of all DAC channels can be driven to a predefined value stored in the preset register by driving the
PRE input low. The PRE input is asynchronous to the clock.
Table 3. CTRL0 Bit Register
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
PD
DO
X
IM
Bit Definitions:
PD
Full Device Power Down.
0 = Normal
1 = Power Down
DO
Digital Output Enable.
0 = Disable
1 = Enable
IM
Input Mode.
0 = Straight Binary
1 = Twos Complement
X
Reserved.
If DOUT is enabled, the data input on DIN is output on DOUT with a 16-cycle delay. This feature makes it
possible to daisy-chain multiple DACs on one serial bus.
Table 4. CTRL1 Bit Register
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
PD
DO
X
IM
Bit Definitions:
PXY
Power Down DACXY. In power-down mode, the amplifiers of the selected DAC pair within the device
are disabled and the total power consumption of the device is significantly reduced. Power-down
mode of a specific DAC pair can be selected by setting the PXY bit within the data word to '1'.
0 = Normal
1 = Power Down
SXY
DACXY Speed Mode. There are two settling time modes: fast and slow. Fast mode of a DAC pair is
selected by setting SXY to '1', and slow mode is selected by setting SXY to '0'.
0 = Slow
1 = Fast
NOTE: XY refers to DAC pair AB, CD, EF, or GH.
10
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