参数资料
型号: TLV5613CDW
厂商: TEXAS INSTRUMENTS INC
元件分类: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 1 us SETTLING TIME, 12-BIT DAC, PDSO20
封装: PLASTIC, SO-20
文件页数: 6/23页
文件大小: 447K
代理商: TLV5613CDW
TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full scale code and the lowest code that produces a positive output voltage.
TLV5613 interfaced to an Intel MCS251 controller
The circuit in Figure 17 shows how to interface the TLV5613 to an Intel MCS251 microcontroller. The address
bus and the data bus of the controller are multiplexed on port 0 (non page mode) to save port pins. To separate
the address bits and the data bits, the controller provides a dedicated signal, address latch enable (ALE), which
is connected to a latch at port 0.
An address decoder is required to generate the chip select signal for the TLV5613. In this example, a simple
3-to-8 decoder (74AC138) is used for the interface as shown in Figure 17. The DAC is memory mapped at
addresses 0x8000/1/2/3 within the data memory address space and mirrored every 32 address locations
(0x8020/1/2/3, 0x8040/1/2/3, etc.). In a typical microcontroller system, programmable logic should be used to
generate the chip select signals for the entire system.
The data pins and the WE pin of the TLV5613 can be connected directly to the multiplexed address and data
bus and the WR signal of the controller.
LDAC is held high so that the output voltage is updated using the RLDAC bit in the control register. Hardware
power down mode is deactivated permanently by pulling PWD to DVDD.
P2 A(15–8)
P0 AD(7–0)
ALE
WR
D(7–0)
A
B
C
G1
G2A
G2B
A1–0)
D(7–0)
CS
WE
REF
REF191
A(15–0)
AD(7–0)
CS(7–0)
DVDD
8
16
8
RL
74AC373
8xC251
74AC138
TLV5613
A15
A2
A3
A4
2
DVDD
Q(7–0)
Y(7–0)
G2A
SPD
PWD
LDAC
LE
OE
OUT
Figure 17. TLV5613 Interfaced to an Intel MCS251 Controller
MCS is a registered trademark of Intel Corporation.
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TLV5613CPWR PARALLEL, WORD INPUT LOADING, 1 us SETTLING TIME, 12-BIT DAC, PDSO20
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