参数资料
型号: TLV5613CPW
厂商: TEXAS INSTRUMENTS INC
元件分类: DAC
英文描述: PARALLEL, WORD INPUT LOADING, 1 us SETTLING TIME, 12-BIT DAC, PDSO20
封装: PLASTIC, TSSOP-20
文件页数: 3/23页
文件大小: 447K
代理商: TLV5613CPW
TLV5613
2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN
SLAS174B – DECEMBER 1997 – REVISED NOVEMBER 2000
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
POWER DOWN SUPPLY CURRENT
vs
TIME
0.00001
0.000001
100
300
t – Time – ms
0.01
0.001
0.0001
200
400
500
0
0.1
1
600
I
DD
Supply
Current
mA
Figure 14
APPLICATION INFORMATION
general function
The TLV5613 is a 12-bit, single supply DAC, based on a resistor string architecture. It consists of a parallel
interface, speed and power down control logic, a resistor string and a rail-to-rail output buffer. The output voltage
(full scale determined by reference) is given by:
2REF
CODE
0x1000
[V]
Where REF is the reference voltage and CODE is the digital input value, range 0x000 to 0xFFF. A power on
reset initially puts the internal latches to a defined state (all bits zero).
parallel interface
The device latches data on the positive edge of WE. It must be enabled with CS low. Whether the data is written
to one of the DAC holding latches (MSW, LSW) or the control register, depends on the address bits A1 and A0.
LDAC low updates the DAC with the value in the holding latch. LDAC is an asynchronous input and can be held
low, if a separate update is not necessary. Two more asynchronous inputs, SPD and PWD control the settling
times and the power down mode:
SPD:
Speed control
1
→ fast mode
0
→ slow mode
PWD:
Power control
1
→ normal operation 0 → power down
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