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参数资料
| 型号： | TLV5623IDGKR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 9 us SETTLING TIME, 8-BIT DAC, PDSO8 |
| 封装： | GREEN, PLASTIC, MSOP-8 |
| 文件页数： | 19/23页 |
| 文件大小： | 578K |
| 代理商： | TLV5623IDGKR |
TLV5623C, TLV5623I
2.7V TO 5.5V LOW POWER 8BIT DIGITALTOANALOG
CONVERTERS WITH POWER DOWN
SLAS231B JUNE 1999 REVISED APRIL 2004
5
WWW.TI.COM
operating characteristics over recommended operating free-air temperature range (unless
otherwise noted)
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ts(FS)
Output settling time, full scale
RL = 10 k,
CL = 100 pF,
Fast
3
5.5
s
ts(FS)
Output settling time, full scale
RL = 10 k,
See Note 11
CL = 100 pF,
Slow
9
20
s
ts(CC)
Output settling time, code to code
RL = 10 k,
CL = 100 pF,
Fast
1
s
ts(CC)
Output settling time, code to code
RL = 10 k,
See Note 12
CL = 100 pF,
Slow
2
s
SR
Slew rate
RL = 10 k,
CL = 100 pF,
Fast
3.6
V/ s
SR
Slew rate
RL = 10 k,
See Note 13
CL = 100 pF,
Slow
0.9
V/
s
Glitch energy
Code transition from 0x7F0 to 0x800
10
nVs
S/N
Signal to noise
fs = 400 KSPS
fout = 1.1 kHz,
57
dB
S/(N+D)
Signal to noise + distortion
fs = 400 KSPS
fout = 1.1 kHz,
RL = 10 k
CL = 100 pF,
49
dB
THD
Total harmonic distortion
RL = 10 k,
CL = 100 pF,
BW = 20 kHz
50
dB
Spurious free dynamic range
BW = 20 kHz
60
dB
NOTES: 11. Settling time is the time for the output signal to remain within
±0.5 LSB of the final measured value for a digital input code change
of 0x020 to 0xFF0 or 0xFF0 to 0x020. Not tested, ensured by design.
12. Settling time is the time for the output signal to remain within
± 0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, ensured by design.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
digital input timing requirements
MIN
NOM
MAX
UNIT
tsu(CSFS)
Setup time, CS low before FS
↓
10
ns
tsu(FSCK)
Setup time, FS low before first negative SCLK edge
8
ns
tsu(C16FS)
Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising
edge of FS
10
ns
tsu(C16CS)
Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising
edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup
time is between the FS rising edge and CS rising edge.
10
ns
twH
Pulse duration, SCLK high
25
ns
twL
Pulse duration, SCLK low
25
ns
tsu(D)
Setup time, data ready before SCLK falling edge
8
ns
th(D)
Hold time, data held valid after SCLK falling edge
5
ns
twH(FS)
Pulse duration, FS high
20
ns
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