- 您现在的位置：买卖IC网 > PDF目录98262 > TLV571IDWRG4 (TEXAS INSTRUMENTS INC) 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 PDF资料下载
参数资料
| 型号： | TLV571IDWRG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| 封装： | GREEN, PLASTIC, SOIC-24 |
| 文件页数： | 24/28页 |
| 文件大小： | 429K |
| 代理商： | TLV571IDWRG4 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页当前第24页第25页第26页第27页第28页
TLV571
2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER
SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
Table 1. Conversion Modes
START OF
CONVERSION
OPERATION
COMMENTS – FOR INPUT
Hardware start
(CSTART)
CR0.D5 = 0
Repeated conversions from AIN
CSTART falling edge to start sampling
CSTART rising edge to start conversion
If in INT mode, one INT pulse generated after each conversion
If in EOC mode, EOC will go high to low at start of conversion, and return high
at end of conversion.
CSTART rising edge must be applied
a minimum of 5 ns before or after CLK
rising edge.
Software start
CR0.D5 = 1
Repeated conversions from AIN
WR rising edge to start sampling initially. Thereafter, sampling occurs at the
rising edge of RD.
Conversion begins after 6 clocks after sampling has begun. Thereafter, if in INT
mode, one INT pulse generated after each conversion
If in EOC mode, EOC will go high to low at start of conversion and return high at
end of conversion.
With external clock, WR and RD rising
edge must be a minimum 5 ns before
or after CLK rising edge.
configure the device
The device can be configured by writing to control registers CR0 and CR1.
Table 2. TLV571 Programming Examples
REGISTER
INDEX
D5
D4
D3
D2
D1
D0
COMMENT
REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
COMMENT
EXAMPLE1
CR0
0
Normal, INT OSC
CR1
0
1
0
Binary
EXAMPLE2
CR0
0
1
0
Power down, EXT OSC
CR1
0
1
0
1
0
2’s complement output
power down
The TLV571 offers two power down modes, auto power down and software power down. This device will
automatically proceed to auto power down mode if RD is not present one clock after conversion. Software power
down is controlled directly by the user by pulling CS to DVDD.
Table 3. Power Down Modes
PARAMETERS/MODES
AUTO POWER DOWN
SOFTWARE POWER DOWN
(CS = DVDD)
Maximum power down dissipation current
1 mA
10
A
Comparator
Power down
Clock buffer
Power down
Control registers
Saved
Minimum power down time
1 CLK
2 CLK
Minimum resume time
1 CLK
2 CLK
相关PDF资料 |
PDF描述 |
|---|---|
| TLV571IDWR | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| TLV571IPWR | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| TLV571IDWG4 | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| TLV571IDW | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
| TLV571IPWG4 | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO24 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TLV571IPW | 功能描述:模数转换器 - ADC 8bit SAR A/D RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TLV571IPWG4 | 功能描述:模数转换器 - ADC 8-Bit 1.25 MSPS Single Ch. RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| TLV571PW | 制造商:TI 制造商全称:Texas Instruments 功能描述:2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT, PARALLEL ANALOG-TO-DIGITAL CONVERTER |
| TLV5734 | 制造商:TI 制造商全称:Texas Instruments 功能描述:TRIPLE 8 BIT 30 MSPS ADC WITH HIGH -PRECISION CLAMP FOR YUV/RGB VIDEO |
| TLV5734PAG | 功能描述:视频模拟/数字化转换器集成电路 8B 30MSPS ADC Triple Ch Digital Clamp RoHS:否 制造商:Texas Instruments 输入信号类型:Differential 转换器数量:1 ADC 输入端数量:4 转换速率:3 Gbps 分辨率:8 bit 结构: 输入电压:3.3 V 接口类型:SPI 信噪比: 电压参考: 电源电压-最大:3.45 V 电源电压-最小:3.15 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:TCSP-48 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。