TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAMMODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
11
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
capacitance over recommended ranges of supply voltage and ambient temperature,
f = 1 MHz (see Note 2)
PARAMETER
’4EP64xxN
MIN
’4EP72xxN
MIN
UNIT
MAX
82
MAX
92
Ci(A)
Ci(OE)
Ci(CAS)
Ci(RAS)
Ci(W)
Co
Ci/o(SDA)
Ci(SPD)
NOTE 2: VDD = NOM supply voltage
±
10%, and the bias on pins under test is 0 V.
Input capacitance, A0–A11
pF
Input capacitance, OEx
58
65
pF
Input capacitance, CASx
16
23
pF
Input capacitance, RASx
58
65
pF
Input capacitance, WEx
58
65
pF
Output capacitance
8
8
pF
Input/output capacitance, SDA input
9
9
pF
Input capacitance, SA0, SA1, SA2, SCL inputs
7
7
pF
switching characteristics over recommended ranges of supply voltage and ambient temperature
(see Note 3)
PARAMETER
’4EP64xxN-50
’4EP72xxN-50
’4EP64xxN-60
’4EP72xxN-60
’4EP64xxN-70
’4EP72xxN-70
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
tAA
tCAC
tCPA
tRAC
tOEA
tCLZ
tREZ
tCEZ
tOEZ
tWEZ
NOTES:
Access time from column address (see Note 4)
25
30
35
ns
Access time from CASx (see Note 4)
13
15
18
ns
Access time from CASx precharge (see Note 4)
28
35
40
ns
Access time from RASx (see Note 4)
50
60
70
ns
Access time from OEx (see Note 4)
13
15
18
ns
Delay time, CASx to output in low impedance
0
0
0
ns
Output buffer turn-off delay from RASx (see Note 5)
3
13
3
15
3
18
ns
Output buffer turn-off delay from CASx (see Note 5)
3
13
3
15
3
18
ns
Output buffer turn-off delay from OEx (see Note 5)
3
13
3
15
3
18
ns
Output buffer turn-off delay from WEx (see Note 5)
3
13
3
15
3
18
ns
3. With ac parameters, it is assumed that tT = 2 ns.
4. Access times are measured with output reference levels of VOH=2 V and VOL=0.8 V.
5. The maximum values of tREZ, tCEZ, tOEZ, and tWEZ are specified when the outputs are no onger driven. Data-in should not be driven
until one of the applicable maximum values is satisfied.