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参数资料
型号： TM893GBK32S-80
厂商： Texas Instruments, Inc.
英文描述： EXTENDED DATA OUT DYNAMIC RAM MODULES
中文描述： 扩展数据输出动态随机存储器模块
文件页数： 10/12页
文件大小： 170K
代理商： TM893GBK32S-80
TM497FBK32, TM497FBK32S 4194304 BY 32-BIT
TM893GBK32, TM893GBK32S 8388608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAMMODULES
SMMS668 – NOVEMBER 1996
10
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’497FBK32-60
’893GBK32-60
MIN
’497FBK32-70
’893GBK32-70
MIN
’497FBK32-80
’893GBK32-80
MIN
UNIT
MAX
MAX
MAX
tRC
tPC
tRASP
tRAS
tCAS
tCP
tRP
tWP
tASC
tASR
tDS
tRCS
tCWL
tRWL
tWCS
tWRP
tCAH
tRHCP
tDH
tRAH
tRCH
tRRH
tWCH
tWRH
tCHR
tCRP
tCSH
tCSR
tRAD
tRAL
tCAL
tRCD
tRPC
tRSH
tREF
tT
NOTES:
Cycle time, random read or write (see Note 7)
110
130
150
ns
Cycle time, page-mode read or write (see Notes 7 and 8)
40
45
50
ns
Pulse duration, page-mode, RAS low
60
100 000
70
100 000
80
100 000
ns
Pulse duration, non-page-mode, RAS low
60
10 000
70
10 000
80
10 000
ns
Pulse duration, CAS low
15
10 000
18
10 000
20
10 000
ns
Pulse duration, CAS high
10
10
10
ns
Pulse duration, RAS high (precharge)
40
50
60
ns
Pulse duration, W low
10
10
10
ns
Setup time, column address before CAS low
0
0
0
ns
Setup time, row address before RAS low
0
0
0
ns
Setup time, data before CAS low
0
0
0
ns
Setup time, W high before CAS low
0
0
0
ns
Setup time, W-low before CAS high
10
12
15
ns
Setup time, W-low before RAS high
10
12
15
ns
Setup time, W-low before CAS low
0
0
0
ns
Setup time, W-high before RAS low (CBR refresh only)
10
10
10
ns
Hold time, column address after CAS low
10
12
15
ns
Hold time, RAS high after CAS precharge
35
40
45
ns
Hold time, data after CAS low
10
12
15
ns
Hold time, row address after RAS low
10
10
10
ns
Hold time, W high after CAS high (see Note 9)
0
0
0
ns
Hold time, W high after RAS high (see Note 9)
0
0
0
ns
Hold time, W low after CAS low
10
12
15
ns
Hold time, W high after RAS low (CBR refresh only)
10
10
10
ns
Delay time, RAS low to CAS high (CBR refresh only)
10
10
10
ns
Delay time, CAS high to RAS low
5
5
5
ns
Delay time, RAS low to CAS high
50
55
60
ns
Delay time, CAS low to RAS low (CBR refresh only)
5
5
5
ns
Delay time, RAS low to column address (see Note 10)
15
30
15
35
15
40
ns
Delay time, column address to RAS high
30
35
40
ns
Delay time, column address to CAS high
30
35
40
ns
Delay time, RAS low to CAS low (see Note 10)
20
45
20
52
20
60
ns
Delay time, RAS high to CAS low (CBR only)
0
0
0
ns
Delay time, CAS low to RAS high
10
12
15
ns
Refresh time interval
32
32
32
ms
Transition time
3
30
3
30
3
30
ns
7. All cycles assume tT = 5 ns.
8. To assure tPC min, tASC should be greater than or equal to tCP.
9. Either tRRH or tRCH must be satisfied for a read cycle.
10. The maximum value is specified only to assure access time.
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