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参数资料
| 型号： | TMC2272AH5C |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | DSP Peripheral |
| 英文描述： | 12-BIT, DSP-VIDEO IMAGING, PPGA120 |
| 封装： | PLASTIC, PGA-120 |
| 文件页数： | 16/20页 |
| 文件大小： | 170K |
| 代理商： | TMC2272AH5C |
TMC2272A
PRODUCT SPECIFICATION
REV. 1.1.3 10/25/00
5
Table 1. Coefcient Loading
Inputs
A11-0
E11, D13, E12,
E13, F11, F12,
F13, G13, G11,
G12, H13, H12
84, 83, 82, 81,
80, 79, 78, 77,
76, 75, 74, 73
Data Input A. This is one of three 12-bit wide data input ports.
B11-0
B10, A11, B11,
C10, A12, B12,
C11, A13, C12,
B13, C13, D12
97, 96, 95, 94,
93, 92, 91, 90,
89, 87, 86, 85
Data Input B. This is one of three 12-bit wide data input ports.
C11-0
A5, C6, B6, A6,
A7, B7, A8, B8,
A9, B9, A10, C9
111, 110, 109,
108, 107, 105,
104, 103, 101,
100, 99, 98
Data Input C. This is one of three 12-bit wide data input ports.
KA9-0
K13, J11, K12,
L13, L12, K11,
M13, M12, L11,
N13
69, 68, 67, 66,
65, 64, 63, 62,
61, 60
Coefficient Input KAX, KAY, or KAZ. These are the 10-bit
wide coefficient input ports. The value at each of these three
inputs will update one coefficient register as selected by the
coefficient write select (CWSEL1-0) on the next clock. See Table
1 and the Functional Block Diagram.
KB9-0
M11, L10, N12,
N11, M10, L9,
N10, M9, N9, L8
59, 58, 57, 56,
55, 54, 53, 52,
51, 50
Coefficient Input KBX, KBY, OR KBZ. These are the 10-bit
wide coefficient input ports. The value at each of these three
inputs will update one coefficient register as selected by the
coefficient write select (CWSEL1-0) on the next clock. See Table
1 and the Functional Block Diagram.
KC9-0
M8, N8, N7, M7,
N6, M6, N5, M5,
N4, L5
49, 48, 47, 45,
44, 43, 41, 40,
39, 38
Coefficient Input KCX, KCY, OR KCZ. These are the 10-bit
wide coefficient input ports. The value at each of these three
inputs will update one coefficient register as selected by the
coefficient write select (CWSEL1-0) on the next clock. See Table
1 and the Functional Block Diagram.
Outputs
X11-0
B4, A3, A2, B3,
A1, C3, B2, B1,
D3, C2, C1, D2
115, 116, 117,
119, 120, 1, 2, 3,
4, 5, 6, 7
Output X. These are the data outputs. Data are available at the
12-bit registered Output Ports X,Y and Z tDO after every clock
rising edge.
Y11-0
D1, E2, E1, F2,
F1, G2, G1, H1,
K1, J2, J1, H2
9, 10, 11, 13, 14,
15, 17, 18, 23,
22, 21, 19
Output Y. These are the data outputs. Data are available at the
12-bit registered Output Ports X,Y and Z tDO after every clock
rising edge.
Z11-0
M4, N3, M3, N2,
M2, L3, N1, L2,
K3, M1, L1, K2
37, 36, 35, 33,
32, 31, 30, 29,
28, 27, 26, 25
Output Z. These are the data outputs. Data are available at the
12-bit registered Output Ports X,Y and Z tDO after every clock
rising edge.
CWSEL1,0
00
01
10
11
Hold
Load
Input
KA9-0
All
KAX
KAY
KAZ
Hold
Load
Input
KB9-0
All
KBX
KBY
KBZ
Hold
Load
Input
KC9-0
All
KCX
KCY
KCZ
Pin Descriptions (continued)
Pin Name
CPGA/PPGA/
MPGA
Pin Number
KE Pin Number
Pin Function Description
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