- 您现在的位置：买卖IC网 > PDF目录382621 > TMP320C6201GFNA100 (Texas Instruments, Inc.) FIXED-POINT DIGITAL SIGNAL PROCESSOR PDF资料下载
参数资料
| 型号： | TMP320C6201GFNA100 |
| 厂商： | Texas Instruments, Inc. |
| 元件分类： | 数字信号处理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 定点数字信号处理器 |
| 文件页数： | 31/70页 |
| 文件大小： | 1050K |
| 代理商： | TMP320C6201GFNA100 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页当前第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E
OCTOBER 1999
REVISED MARCH 2004
31
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
power-supply sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time if the other
supply is below the proper operating voltage.
system-level design considerations
System-level design considerations, such as bus contention, may require supply sequencing to be
implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered
down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the
output buffers are powered up, thus, preventing bus contention with other chips on the board.
power-supply design considerations
For systems using the C6000
DSP platform of devices, the core supply may be required to provide in excess
of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic
within the DSP(s) and is corrected once the CPU sees an internal clock pulse. With the PLL enabled, as the
I/O supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the
PLL disabled, as many as five external clock cycle pulses may be required to stop this extra current draw. A
normal current state returns once the I/O power supply is turned on and the CPU sees a clock pulse. Decreasing
the amount of time between the core supply power up and the I/O supply power up can minimize the effects
of this current draw.
A dual-power supply with simultaneous sequencing, such as that available with TPS563xx controllers or
PT69xx plug-in power modules, can be used to eliminate the delay between core and I/O power up [see the
Using the TPS56300 to Power DSPs
application report (literature number SLVA088)]. A Schottky diode can also
be used to tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize
the logic within the DSP.
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000
platform of DSPs, the PC board should include separate power planes for
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
相关PDF资料 |
PDF描述 |
|---|---|
| TMP320C6201GGP100 | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| TMP320C6201GGP120 | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| TMP320C6201GGPA100 | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| TMP320C6201GHK120 | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| TMP320C6201GHKA100 | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
相关代理商/技术参数 |
参数描述 |
|---|---|
| TMP320C6201GGP100 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| TMP320C6201GGP120 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| TMP320C6201GGPA100 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| TMP320C6201GHK120 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| TMP320C6201GHKA100 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
发布紧急采购，3分钟左右您将得到回复。