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参数资料
| 型号： | TMP320C6202BGHKA100 |
| 厂商： | Texas Instruments, Inc. |
| 元件分类： | 数字信号处理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 定点数字信号处理器 |
| 文件页数： | 17/70页 |
| 文件大小： | 1050K |
| 代理商： | TMP320C6202BGHKA100 |
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TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E
OCTOBER 1999
REVISED MARCH 2004
17
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
Signal Descriptions (Continued)
SIGNAL
TYPE
DESCRIPTION
NAME
NO.
EMIF
DATA (CONTINUED)
ED8
ED7
ED6
ED5
ED4
ED3
ED2
ED1
ED0
M17
N19
P19
N15
P18
P17
R19
R18
R17
I/O/Z
External data
EMIF
ASYNCHRONOUS MEMORY CONTROL
Asynchronous memory read-enable
Asynchronous memory output-enable
Asynchronous memory write-enable
Asynchronous memory ready input
EMIF
SYNCHRONOUS DRAM (SDRAM)/SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL
U19
O/Z
SDRAM address 10 (separate for deactivate command)
V19
O/Z
SDRAM column-address strobe/SBSRAM address strobe
U18
O/Z
SDRAM row-address strobe/SBSRAM output-enable
T17
O/Z
SDRAM write-enable/SBSRAM write-enable
EMIF
BUS ARBITRATION
P14
I
Hold request from the host
V15
O
Hold-request-acknowledge to the host
TIMER 0
E5
O
Timer 0 or general-purpose output
C5
I
Timer 0 or general-purpose input
Timer 1
A5
O
Timer 1 or general-purpose output
B5
I
Timer 1 or general-purpose input
DMA ACTION COMPLETE STATUS
A17
B17
C16
A18
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
A12
I
External clock source (as opposed to internal)
B9
I/O/Z
Receive clock
C9
I/O/Z
Transmit clock
A10
I
Receive data
B10
O/Z
Transmit data
E10
I/O/Z
Receive frame sync
A9
I/O/Z
Transmit frame sync
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
ARE
AOE
AWE
ARDY
U14
W14
V14
W15
O/Z
O/Z
O/Z
I
SDA10
SDCAS/SSADS
SDRAS/SSOE
SDWE/SSWE
HOLD
HOLDA
TOUT0
TINP0
TOUT1
TINP1
DMAC3
DMAC2
DMAC1
DMAC0
O
DMA action complete
CLKS0
CLKR0
CLKX0
DR0
DX0
FSR0
FSX0
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相关代理商/技术参数 |
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| TMP320C6202BGJC100 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
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| TMP320C6202BGJL100 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
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