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| 型号： | TMP320R2812PBKA |
| 厂商： | Texas Instruments, Inc. |
| 元件分类： | 数字信号处理 |
| 英文描述： | TMS320R2811, TMS320R2812 Digital Signal Processors |
| 中文描述： | TMS320R2811，TMS320R2812数字信号处理器 |
| 文件页数： | 32/147页 |
| 文件大小： | 2021K |
| 代理商： | TMP320R2812PBKA |
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Functional Overview
32
June 2004
SPRS257
Generally, the priority of memory bus accesses can be summarized as follows:
Highest:
Data Writes (Simultaneous data and program writes cannot occur
on the memory bus.)
Program Writes (Simultaneous data and program writes cannot occur
on the memory bus.)
Data Reads
Program Reads (Simultaneous program reads and fetches cannot occur
on the memory bus.)
Lowest:
Fetches
(Simultaneous program reads and fetches cannot occur
on the memory bus.)
3.2.3
Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, R281x
adopts a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the
various busses that make up the processor “Memory Bus” into a single bus consisting of 16 address lines and
16 or 32 data lines and associated control signals. Two versions of the peripheral bus are supported on R281x.
One version only supports 16-bit accesses (called peripheral frame 2) and this retains compatibility with
C240x-compatible peripherals. The other version supports both 16- and 32-bit accesses (called peripheral
frame 1).
3.2.4
Real-Time JTAG and Analysis
R281x implements the standard IEEE 1149.1 JTAG interface. Additionally, R281x supports real-time mode
of operation whereby the contents of memory, peripheral and register locations can be modified while the
processor is running and executing code and servicing interrupts. The user can also single step through
non-time critical code while enabling time-critical interrupts to be serviced without interference. R281x
implements the real-time mode in hardware within the CPU. This is a unique feature to R281x, no software
monitor is required. Additionally, special analysis hardware is provided which allows the user to set hardware
breakpoint or data/address watch-points and generate various user selectable break events when a match
occurs.
3.2.5
External Interface (XINTF) (2812 Only)
This asynchronous interface consists of 19 address lines, 16 data lines, and three chip-select lines. The
chip-select lines are mapped to five external zones, Zones 0, 1, 2, 6, and 7. Zones 0 and 1 share a single
chip-select; Zones 6 and 7 also share a single chip-select. Each of the five zones can be programmed with
a different number of wait states, strobe signal setup and hold timing and each zone can be programmed for
extending wait states externally or not. The programmable wait-state, chip-select and programmable strobe
timing enables glueless interface to external memories and peripherals.
3.2.6
M0, M1 SARAMs
All C28x devices contain these two blocks of single access memory, each 1K x 16 in size. The stack pointer
points to the beginning of block M1 on reset. The M0 block overlaps the 240x device B0, B1, B2 RAM blocks
and hence the mapping of data variables on the 240x devices can remain at the same physical address on
C28x devices. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both
program and data space. Hence, the user can use M0 and M1 to execute code or for data variables. The
partitioning is performed within the linker. The C28x device presents a unified memory map to the programmer.
This makes for easier programming in high-level languages.
3.2.7
L0, L1, L2, L3, H0 SARAMs
R281x contains an additional 18K x 16 of single-access RAM (SARAM), divided into 5 blocks (4K + 4K +1K
+1K+ 8K). Each block can be independently accessed, minimizing pipeline stalls. Each block is mapped to
both program and data space.
A
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