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参数资料
| 型号： | TMS27PC512-20FML |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | PROM |
| 英文描述： | 64K X 8 OTPROM, 200 ns, PQCC32 |
| 封装： | 0.050 INCH PITCH, PLASTIC PACKAGE-32 |
| 文件页数： | 12/13页 |
| 文件大小： | 208K |
| 代理商： | TMS27PC512-20FML |
TMS27C512 65536 BY 8BIT UV ERASABLE
TMS27PC512 65536 BY 8BIT
PROGRAMMABLE READONLY MEMORIES
SMLS512G NOVEMBER 1985 REVISED SEPTEMBER 1997
8
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
switching characteristics over recommended ranges of operating conditions
PARAMETER
TEST CONDITIONS
(SEE NOTES 3 AND 4)
’27C512-10
’27PC512-10
’27C512-12
’27PC512-12
UNIT
PARAMETER
(SEE NOTES 3 AND 4)
MIN
MAX
MIN
MAX
UNIT
ta(A)
Access time from address
100
120
ns
ta(E)
Access time from chip enable
CL = 100 pF,
100
120
ns
ten(G)
Output enable time from G /VPP
CL = 100 pF,
1 Series 74 TTL Load,
55
ns
tdis
Output disable time from G /VPP or E, whichever occurs first
1 Series 74 TTL Load,
Input tr ≤ 20 ns,
Input tf ≤ 20 ns
0
45
0
45
ns
tv(A)
Output data valid time after change of address, E, or G /VPP,
whichever occurs first
r
Input tf ≤ 20 ns
0
ns
PARAMETER
TEST CONDITIONS
(SEE NOTES 3 AND 4)
’27C512-15
’27PC512-15
UNIT
PARAMETER
(SEE NOTES 3 AND 4)
MIN
MAX
UNIT
ta(A)
Access time from address
150
ns
ta(E)
Access time from chip enable
CL = 100 pF,
150
ns
ten(G)
Output enable time from G /VPP
CL = 100 pF,
1 Series 74 TTL Load,
75
ns
tdis
Output disable time from G /VPP or E, whichever occurs first
1 Series 74 TTL Load,
Input tr ≤ 20 ns,
Input tf ≤ 20 ns
0
60
ns
tv(A)
Output data valid time after change of address, E, or G /VPP, whichever
occurs first
r
Input tf ≤ 20 ns
0
ns
PARAMETER
TEST CONDITIONS
(SEE NOTES 3 AND 4)
’27C512-20
’27PC512-20
’27C512-25
’27PC512-25
UNIT
PARAMETER
(SEE NOTES 3 AND 4)
MIN
MAX
MIN
MAX
UNIT
ta(A)
Access time from address
200
250
ns
ta(E)
Access time from chip enable
CL = 100 pF,
200
250
ns
ten(G)
Output enable time from G /VPP
CL = 100 pF,
1 Series 74 TTL Load,
75
100
ns
tdis
Output disable time from G /VPP or E, whichever occurs first
1 Series 74 TTL Load,
Input tr ≤ 20 ns,
Input tf ≤ 20 ns
0
60
0
60
ns
tv(A)
Output data valid time after change of address, E, or G /VPP,
whichever occurs first
r
Input tf ≤ 20 ns
0
ns
Value calculated from 0.5 V delta to measured output level. This parameter is only sampled.
NOTES:
3. For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low (see Figure 2).
4. Common test conditions apply for tdis except during programming.
switching characteristics for programming: VCC = 6.50 V and G/VPP = 13 V (SNAP! Pulse),
TA = 25°C (see Note 3)
PARAMETER
MIN
MAX
UNIT
tdis(G)
Disable time, output from G /VPP
0
130
ns
NOTE 3: For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low.
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相关代理商/技术参数 |
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| TMS27PC512-20FML4 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 EPROM |
| TMS27PC512-20NE | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 EPROM |
| TMS27PC512-20NE4 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:x8 EPROM |
| TMS27PC51220NL | 制造商:TI 功能描述:* |
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