参数资料
| 型号： | TMS320C6205GHKA200 |
| 厂商： | Texas Instruments |
| 文件页数： | 43/73页 |
| 文件大小： | 0K |
| 描述： | IC FIXED-POINT DSP 288-BGA |
| 标准包装： | 90 |
| 系列： | TMS320C62x |
| 类型： | 定点 |
| 接口： | McBSP，PCI |
| 时钟速率： | 200MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 128kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.50V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 288-LFBGA |
| 供应商设备封装： | 288-BGA Microstar（16x16） |
| 包装： | 托盘 |
| 其它名称： | 296-32744 TMS320C6205GHKA200-ND |
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TMS320C6205
FIXEDPOINT DIGITAL SIGNAL PROCESSOR
SPRS106G OCTOBER 1999 REVISED JULY 2006
48
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
RESET TIMING
timing requirements for reset (see Figure 28)
NO.
200
UNIT
NO.
MIN
MAX
UNIT
1
tw(RST)
Width of the RESET pulse (PLL stable)
10P
ns
1
tw(RST)
Width of the RESET pulse (PLL needs to sync up)§
250
s
10
tsu(ED)
Setup time, ED boot configuration bits valid before RESET high
5P#
ns
11
th(ED)
Hold time, ED boot configuration bits valid after RESET high
5P
ns
This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4, x6, x7, x8, x9, x10, and x11 when CLKIN and PLL
are stable.
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§ This parameter applies to CLKMODE x4, x6, x7, x8, x9, x10, and x11 only. The RESET signal is not connected internally to the Clock PLL circuit.
The PLL requires a minimum of 250
s to stabilize following device power up or after PLL configuration has been changed. During that time,
RESET must be asserted to ensure proper device operation. See the clock PLL section for power up (specifically Figure 5, Note E) and for PLL
lock times (Table 4).
ED[31:0] are the boot configuration pins during device reset.
# A 250 s setup time before the rising edge of RESET is required when using CLKMODE x4, x6, x7, x8, x9, x10, or x11.
switching characteristics over recommended operating conditions during reset|| (see Figure 28)
NO.
PARAMETER
200
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
2
td(RSTL-CKO2IV)
Delay time, RESET low to CLKOUT2 invalid
P
ns
3
td(RSTH-CKO2V)
Delay time, RESET high to CLKOUT2 valid
4P
ns
4
td(RSTL-HIGHIV)
Delay time, RESET low to high group invalid
P
ns
5
td(RSTH-HIGHV)
Delay time, RESET high to high group valid
4P
ns
6
td(RSTL-LOWIV)
Delay time, RESET low to low group invalid
P
ns
7
td(RSTH-LOWV)
Delay time, RESET high to low group valid
4P
ns
8
td(RSTL-ZHZ)
Delay time, RESET low to Z group high impedance
P
ns
9
td(RSTH-ZV)
Delay time, RESET high to Z group valid
4P
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
|| High group consists of:
HOLDA
Low group consists of:
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1, XSP_CLK, XSP_DO, and XSP_CS
Z group consists of:
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,
SDA10,
CLKX0,
CLKX1,
FSX0,
FSX1,
DX0,
DX1,
CLKR0,
CLKR1,
FSR0,
FSR1,
AD[31:0],
PCBE[3:0], PINTA, PREQ, PSERR, PPERR, PDEVSEL, PFRAME, PIRDY, PPAR, PSTOP, PTRDY, and PME
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相关代理商/技术参数 |
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| TMS320C6205GJC100 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
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| TMS320C6205ZHK200 | 功能描述:数字信号处理器和控制器 - DSP, DSC Fixed-Pt Dig Sig Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
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