收藏本站
参数资料
型号： TMS320C6414TBGLZA7
厂商： Texas Instruments
文件页数： 97/146页
文件大小： 0K
描述： IC FIXED-POINT DSP 532-FCBGA
标准包装： 60
系列： TMS320C6414T/15T/16T
类型： 定点
接口： 主机接口，McBSP，PCI，UTOPIA
时钟速率： 720MHz
非易失内存： 外部
芯片上RAM： 1.03MB
电压 - 输入/输出： 3.30V
电压 - 核心： 1.20V
工作温度： -40°C ~ 105°C
安装类型： 表面贴装
封装/外壳： 532-BFBGA，FCBGA
供应商设备封装： 532-FCBGA（23x23）
包装： 托盘
配用： TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
54
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Terminal Functions (Continued)
SIGNAL
TYPE
IPD/
DESCRIPTION
NAME
NO.
TYPE
IPD/
IPU
DESCRIPTION
UTOPIA SLAVE (ATM CONTROLLER) TRANSMIT INTERFACE (CONTINUED)
UXDATA7Y
AD10
UXDATA6Y
AD9
UXDATA5Y
AD8
8-bit Transmit Data Bus
Using the Transmit Data Bus, the UTOPIA Slave (on the rising edge of the UXCLK) transmits
UXDATA4Y
AE8
O/Z
8-bit Transmit Data Bus
Using the Transmit Data Bus, the UTOPIA Slave (on the rising edge of the UXCLK) transmits
the 8-bit ATM cells to the Master ATM Controller.
UXDATA3Y
AF9
O/Z
the 8-bit ATM cells to the Master ATM Controller.
When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), these pins are tied-
UXDATA2Y
AF7
When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), these pins are tied-
off.
UXDATA1Y
AE7
off.
UXDATA0Y
AD7
UTOPIA SLAVE (ATM CONTROLLER) RECEIVE INTERFACE
URCLKY
AD12
I
h
Source clock for UTOPIA receive driven by Master ATM Controller.
When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off.
URCLAVY
AF14
O/Z
Receive cell available status output signal from UTOPIA Slave.
0
indicates NO space is available to receive a cell from Master ATM Controller
1
indicates space is available to receive a cell from Master ATM Controller
When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off.
URENBY
AD15
I
UTOPIA receive interface enable input signal. Asserted by the Master ATM Controller to indi-
cate to the UTOPIA Slave to sample the Receive Data Bus (URDATA[7:0]) and URSOC signal
in the next clock cycle or thereafter.
When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off.
URSOCY
AB14
I
h
Receive Start-of-Cell signal. This signal is output by the Master ATM Controller to indicate to
the UTOPIA Slave that the first valid byte of the cell is available to sample on the 8-bit Receive
Data Bus (URDATA[7:0]).
When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off.
CLKX1/
URADDR4§
AB12
I/O/Z
McBSP1 [default] or UTOPIA receive address pins
As UTOPIA receive address pins URADDR[4:0] (I), UTOPIA_EN (BEA11 pin) = 1:
CLKS1/
URADDR3§
AC8
I
As UTOPIA receive address pins URADDR[4:0] (I), UTOPIA_EN (BEA11 pin) = 1:
5-bit Slave receive address input pins driven by the Master ATM Controller to identify and
select one of the Slave devices (up to 31 possible) in the ATM System.
CLKR1/
URADDR2§
AC10
I/O/Z
select one of the Slave devices (up to 31 possible) in the ATM System.
URADDR1 and URADDR0 pins are tied off when the UTOPIA peripheral is disabled
[UTOPIA_EN (BEA11 pin) = 0]
URADDR1Y
AF10
I
[UTOPIA_EN (BEA11 pin) = 0]
For the McBSP1 pin functions (UTOPIA_EN (BEA11 pin) = 0 [default]), see the
URADDR0Y
AE10
I
For the McBSP1 pin functions (UTOPIA_EN (BEA11 pin) = 0 [default]), see the
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) section of this table.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§ These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
hExternal pulldowns required: If UTOPIA is selected (BEA11 = 1) and these pins are connected to other devices, then a 10-k resistor must be
used to externally pull down each of these pins. If these pins are “no connects”, then only UXCLK and URCLK need to be pulled down and other
pulldowns are not necessary.
External pullups required: If UTOPIA is selected (BEA11 = 1) and these pins are connected to other devices, then a 10-k resistor must be used
to externally pull up each of these pins. If these pins are “no connects”, then the pullups are not necessary.
ΨThe C6414T device does not support the UTOPIA peripheral; therefore, these standalone UTOPIA pins are Reserved (leave unconnected, do
not connect to power or ground) with the exception of UXCLK and URCLK which should be connected to a 10-k
pulldown resistor (see the
square [
h] footnote).
相关PDF资料
PDF描述
HK50A-12/A PWR SUP IND LOW PRO 12V 4.2A
RMM36DTBH CONN EDGECARD 72POS R/A .156 SLD
VE-B3J-CY-F1 CONVERTER MOD DC/DC 36V 50W
2209-V-RC INDUCTOR TORD HI AMP 47UH VERT
GEC06DRAN CONN EDGECARD 12POS R/A .100 SLD
相关代理商/技术参数
参数描述
TMS320C6414TBGLZA8 功能描述:数字信号处理器和控制器 - DSP, DSC Fixed-Pt Dig Signal Processor RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
TMS320C6414TBGLZW6 制造商:Texas Instruments 功能描述:
TMS320C6414TBGLZW7 制造商:Texas Instruments 功能描述:
TMS320C6414TBZLZ1 功能描述:数字信号处理器和控制器 - DSP, DSC Fixed-Pt Dig Signal Processor RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
TMS320C6414TBZLZ1 制造商:Texas Instruments 功能描述:IC FIXED-PT DSP 64BIT 1GHZ FCBGA-532
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*