参数资料
型号: TMS320C6414TZLZ7
厂商: Texas Instruments
文件页数: 143/146页
文件大小: 0K
描述: IC DSP FIXED-POINT 532-FCBGA
标准包装: 60
系列: TMS320C6414T/15T/16T
类型: 定点
接口: 主机接口,McBSP,PCI,UTOPIA
时钟速率: 720MHz
非易失内存: 外部
芯片上RAM: 1.03MB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: 0°C ~ 90°C
安装类型: 表面贴装
封装/外壳: 532-BFBGA,FCBGA
供应商设备封装: 532-FCBGA(23x23)
包装: 托盘
配用: TMDXEVM6452-ND - TMDXEVM6452
296-23038-ND - DSP STARTER KIT FOR TMS320C6416
其它名称: 296-19386
TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M NOVEMBER 2003 REVISED APRIL 2009
96
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
SYNCHRONOUS DRAM TIMING (CONTINUED)
ECLKOUTx
CEx
ABE[7:0] or BBE[1:0]
AEA[12:3] or BEA[10:1]
AED[63:0] or BED[15:0]
AEA13 or BEA11
AOE/SDRAS/SOE
ARE/SDCAS/SADS/SRE
AWE/SDWE/SWE
AEA[22:14] or BEA[20:12]
BE1
BE2
BE3
BE4
Bank
Column
D1
D2
D3
D4
8
7
6
5
1
3
2
8
4
1
READ
PDT§
14
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
§ PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter RAM). For PDT read, data
is not latched into EMIF. The PDTRL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data
phase of a read transaction. The latency of the PDT signal for a read can be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10, or 11,
respectively. PDTRL equals 00 (zero latency) in Figure 27.
Figure 27. SDRAM Read Command (CAS Latency 3) for EMIFA and EMIFB
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