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P
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A–APRIL 2006–REVISED DECEMBER 2006
Table 2-3. Terminal Functions (continued)
SIGNAL
NAME
TYPE
(1)
IPD/IPU
(2)
DESCRIPTION
NO.
EMIFA (64-BIT) - ADDRESS
EMIFA external address (word address) (
O/Z
)
Controls initialization of the DSP modes at reset (
I
) via pullup/pulldown resistors
[For more detailed information, see
Section 3
,
Device Configuration
.]
Note:
If a configuration pin must be routed out from the device, the internal
pullup/pulldown (IPU/IPD) resistor should not be relied upon; TI recommends
the use of an external pullup/pulldown resistor.
AEA19/BOOTMODE3
AEA18/BOOTMODE2
AEA17/BOOTMODE1
AEA16/BOOTMODE0
AEA15/AECLKIN_SEL
AEA14/HPI_WIDTH
AEA13/LENDIAN
AEA12
N25
L26
L25
P26
P27
R25
R27
R28
O/Z
IPD
Boot mode - device boot mode configurations (BOOTMODE[3:0]) [
Note:
the peripheral
must
be enabled to use the particular boot mode.]
AEA[19:16]
:
0000 - No boot (default mode)
0001 - Host boot (HPI)
0010 -Reserved
0011 - Reserved
0100 - EMIFA 8-bit ROM boot
0101 - Master I2C boot
0110 - Slave I2C boot
0111 - Host boot (PCI)
1000 thru 1111 - Reserved
For more detailed information on the boot modes, see
Section 2.4
,
Boot
Sequence
.
CFGGP[2:0] pins must be set to 000b during reset for proper operation of
the PCI boot mode.
EMIFA input clock source select
Clock mode select for EMIFA (AECLKIN_SEL)
AEA15
:
0 - AECLKIN (default mode)
1 - SYSCLK4 (CPU/x) Clock Rate. The SYSCLK4 clock rate is software
selectable via the Software PLL1 Controller. By default, SYSCLK4 is
selected as CPU/8 clock rate.
HPI peripheral bus width (HPI_WIDTH) select
[Applies only when HPI is enabled; PCI_EN pin = 0]
AEA14
:
0 - HPI operates as an HPI16 (default). (HPI bus is 16 bits wide. HD[15:0]
pins are used and the remaining HD[31:16] pins are reserved pins in the
Hi-Z state.)
1 - HPI operates as an HPI32.
Device Endian mode (LENDIAN)
AEA13
:
0 - System operates in Big Endian mode
1 - System operates in Little Endian mode(default)
O/Z
IPU
O/Z
IPD
AEA11
T25
Note:
For proper C6454 device operation, the
AEA12
and
AEA11
pins
must
be externally pulled down with a 1-k
resistor at device reset.
Device Overview
28
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